WEBVTT 00:00.860 --> 00:04.280 So we'll start with an or so on the edge. 00:05.030 --> 00:08.610 So on the edge, we have an eye socket. 00:09.020 --> 00:11.100 So we have an ICU. 00:12.070 --> 00:13.450 Locks which are present. 00:14.510 --> 00:19.820 OK, on all the edges, they may be present depending on the chip package that you are utilizing. 00:20.120 --> 00:23.400 OK, so we have an array of blocks that are present on an edge. 00:23.670 --> 00:30.650 OK, and then we have and logic blocks which are used to implement the logic functionality. 00:30.860 --> 00:39.080 And for Xilinx FPGA, the art of design configurable, what you learned assume that there are four configurable 00:39.080 --> 00:42.650 logic blocks that we are designing. 00:42.670 --> 00:42.860 Right. 00:42.920 --> 00:47.480 So that we do that we are discussing consist of a food logic block. 00:49.480 --> 00:57.160 OK, and then finally, to implement complex equations or complex functionality, we would really be 00:57.160 --> 01:01.590 having an interconnection between this specific CLB. 01:02.170 --> 01:07.390 So that is handled entirely by an switching matrix or any interconnection. 01:07.820 --> 01:14.320 So this are the interconnection metric which handed the connection between this to Silvis, this to 01:14.500 --> 01:16.580 have a complex functionality. 01:16.580 --> 01:16.790 Right. 01:16.990 --> 01:24.590 Now let's understand what is inside a CLB So inside a CLB, we have multiple slices. 01:24.660 --> 01:32.860 OK, so we have multiple slices, but they are also not a fundamental component which are used to use 01:32.860 --> 01:36.250 to develop a logic inside an FPGA. 01:36.580 --> 01:40.690 So each slice can have multiple. 01:41.930 --> 01:50.090 And so finally, Angellotti is something which is a fundamental block behind designing and developing, 01:50.360 --> 01:53.730 and zaitchik functions on a future. 01:54.440 --> 02:01.550 So we haven't let us assume that we have to input Lutece to input Lutece. 02:01.700 --> 02:09.290 So these are some simple single Strand says, OK, so to input basically if you consider two input. 02:09.300 --> 02:10.950 So we have four unique values. 02:10.970 --> 02:14.930 OK, so that will be four memory location that will be present inside. 02:14.930 --> 02:15.850 And they do this right. 02:15.890 --> 02:16.160 So. 02:17.150 --> 02:23.330 Let us assume that we have an alibi, which consists of a four location. 02:24.660 --> 02:29.170 So then we have a few that are coming out of this. 02:30.240 --> 02:36.780 So these are the symbolism where we can either save one order so we can store one or two inside the 02:36.790 --> 02:42.090 system and then let us assume that we have connected and mux over here. 02:42.360 --> 02:49.710 So it is basically fortressed when monks OK, and then we can decide whether to have a combination of 02:49.720 --> 02:52.630 circuit or to implement the sequences. 02:53.220 --> 02:56.030 So in that case, we're required to have flipflopped. 02:56.030 --> 03:00.990 So we also have flip flop so you can decide which path to follow. 03:01.020 --> 03:07.830 So you again can add one looks and then you can either take this combination output and then you can 03:07.830 --> 03:10.810 also have a provision prior to sequential output. 03:10.830 --> 03:15.730 And finally, you feed this to and I block it. 03:16.260 --> 03:19.860 So this is what a simple destructiveness. 03:20.280 --> 03:24.810 OK, so now slices the slices can have multiple Allardice. 03:25.080 --> 03:27.420 Now these can have different capabilities. 03:27.420 --> 03:36.150 So for example, for an effigy which are belonging to a version less than seven series, they all have 03:36.150 --> 03:37.740 a food input. 03:37.950 --> 03:39.790 It looks OK. 03:39.930 --> 03:46.680 So when you see food input, so basically you have 16 memory location where you can store a single big 03:46.890 --> 03:51.280 one or zero and then you have full control pins. 03:51.570 --> 03:53.250 So here since we have four. 03:54.960 --> 04:00.930 Connection or food inputs for a mux, we can have a selection of, say, stupid right now to implement 04:00.930 --> 04:03.910 a logic functionality is is pretty interesting. 04:03.930 --> 04:12.590 So, for example, let's assume that we wish to implement this function y equals to EB if we just or 04:12.600 --> 04:16.050 if I just go to the next step to discuss more on this. 04:16.090 --> 04:20.160 OK, so let's assume that we are implementing a combination of toked. 04:22.510 --> 04:26.740 OK, and we have an equation like this, Y equals two. 04:27.880 --> 04:33.830 So here now if I just make a table out of this equation, so it becomes very simple. 04:33.850 --> 04:41.380 So we have a B and then we have Y so big and powerful combination, one zero and one. 04:41.830 --> 04:45.250 So we know that when one spell the end, we are one. 04:45.250 --> 04:50.910 We should send Y to the rest of the cases we have C.. 04:51.670 --> 05:01.240 So if you considered OK, so if it consists of doing utility, ok, do it consists of brutality. 05:01.870 --> 05:06.100 We have a food location which are further connected to mux. 05:06.100 --> 05:06.430 Right. 05:06.730 --> 05:10.980 And then the select line basically feeding to an input rate. 05:11.320 --> 05:17.410 And then since this is a combination of circuit two will follow, we, we can exert influence over the 05:17.410 --> 05:18.040 rest of the thing. 05:18.040 --> 05:23.340 And then this is going to block an output by where we have assumed that we have connected. 05:23.350 --> 05:28.840 And so now we know that we will be connected and be here. 05:29.200 --> 05:31.780 So once and we both one. 05:31.780 --> 05:33.640 So we'll be selecting this location. 05:33.640 --> 05:33.870 Right. 05:33.880 --> 05:36.550 And in that case, we wondered why should be close. 05:36.730 --> 05:44.600 And so for that reason, if we just feed one or two here and if we program the rest of the bits for 05:44.620 --> 05:49.330 the cell to be zero, we knew that then one two four zero zero here. 05:49.360 --> 05:53.380 So this the content that we have with this cell will be selected. 05:53.650 --> 05:57.530 We'll be getting close to zero if we apply 012 here. 05:57.550 --> 06:01.270 So this content will be given out on an YPO. 06:01.330 --> 06:02.620 Still will be getting through. 06:02.960 --> 06:06.180 If you apply one zero, we will still be getting zero. 06:06.190 --> 06:12.220 But once we apply one one, this self-contained will be sent to invite and we'll be getting one. 06:12.820 --> 06:19.810 So this is how simple logic operates in the next question comes is how you. 06:23.330 --> 06:28.560 So this is what is happening when we are performing or when we are programming. 06:29.150 --> 06:33.380 So when you are programming or doing your configuration of an object. 06:33.740 --> 06:41.270 So one of the things that happens is all the stem cells, depending on the logic that are implemented, 06:41.620 --> 06:44.360 are being initialized to the required logic. 06:44.610 --> 06:51.320 So if I assume that you are implementing this function on an FPGA to one of the elements which will 06:51.320 --> 06:58.340 be selected out of the slices, the number of slices present on that FPGA, depending on Diable that 06:58.340 --> 07:05.450 you have specified in the industry, and then this contained will be written in a configuration Stipek. 07:05.720 --> 07:12.200 So when we run our application, we'll be having this content will always be a fix and we'll just be 07:12.200 --> 07:13.750 changing A and B this. 07:13.790 --> 07:15.710 And according to that, you'll be getting a value. 07:16.250 --> 07:16.470 OK. 07:16.520 --> 07:20.810 So now you understand one of the processes that happened during the configuration of programming will 07:21.050 --> 07:29.510 often produce the same basis which are used to implement and are being updated with the value depending 07:29.510 --> 07:31.640 on the logic function that you are implementing. 07:32.010 --> 07:35.810 Other key points that you can notice. 07:37.340 --> 07:45.110 The fundamental blocks that are used to implement a logic function inside an FPGA is and, you know, 07:45.320 --> 07:50.500 there may be multiple ill-suited inside a slice and then we have a seal. 07:50.540 --> 07:54.540 So there may be multiple slices that are present inside seal. 07:55.100 --> 08:02.510 So if you just go to an architecture so we have a CLB, which is a block that is used to implement the 08:02.510 --> 08:04.680 logic functionality on. 08:04.700 --> 08:07.880 And if you do so, CLV consists of multiple slices.