So the good thing about the multiplexed is so the along with the retail sector can be helped to implement
the logic function so we can use them to implement conventional logic function.
So let us try to understand some of the fundamentals so that we can proceed to an actual leadership,
because in an FPGA we have different type of multiplexed and that can be used to implement different
combinations of logic and that we have a restriction on the number of input that we can actually feed
to an entity.
So to understand that, we consider a very simple example.
So, for example, let's assume you have this mix, right?
So you have two is two one mux.
OK, now, since we have two inputs, OK, so we have a select single select line which is having a
size of a single bit, and then we have this output line.
Right now, if you consider that this is you, we can take the issue here, which is one of the variable
inside of a function and be here.
Right.
So if we have this kind of configuration, so here y will be equal to Y will be equal to if you know,
since this is and this is connected to a zero.
So Y will be close to it, but right to when we will be having values in zero.
So ever.
And that is multiplied with the V and for the next case it will be to be right now we already know that
as an input, so we cannot connect any variable because we have an altitude here.
So if you remember the structure, we have an L.A. where we'll be studying a single bit and then we
have a mux.
Right.
So this is a typical structure, often slice inciting a feature.
So we cannot we cannot connect a variable here.
So in that case, there is a room that this can only take a value of.
One, two.
OK, so we can have any one or two value here.
So the number of input that we can connect actually with an entity and the structure that we have inside
a slice of an FPGA is only one.
Right?
If we consider the normal logic family or a normal digital circuits, we can actually going to agree
with one of the variable over here available here.
But with the architecture that we have fought in FPGA since we already have any luteal here, we.
Do not have any other choice to connect only a single variable.
All right, so the number of select line they're operating on, the mux decide how many inputs you can
feed to a specific.
And right now we can go to shoot and understand more on this.
Right.
So here we are inside a Spartan 60.
OK, so this is one of the structure of a slate, so you can notice we have a slice.
And then here I'll be noticing that we have a bus which is having the size of six bitrate.
So these are basically the select line that are present on the mux, which is present afternoon.
So we can connect six in pulldown here then.
We have one more, Élodie, which again consists of a six inputs so we can actually succeed here.
OK, and then finally to select this, we have an F seven B Muxtape.
So inside a single space utilizing two Elwood's, we can actually fit 12 inputs and considering one
more select line that we get out of seven B mux, we have in total 13 inputs that can be connected to
that can actually be connected over here or it can actually be used eight to one.
So these are two possibilities are that either you can feed a 13.
So if you utilize this F seven, B, instead of having the six input logic function, you can actually
extend it to 13 the logic function.
OK, so this is how you extend your capabilities.
And then again, you have the capability to actually distribute output.
So that is also possible.
OK, so each slice it slice actually consists of four legs, OK, and each is capable of handling six
inputs.
OK, so you'll be noticing you can have two independently.
This one looks out of a slice or you can actually have a 13 to 13 with input functions that can be actually
implemented out of this slice.
Or if you do consist of other books such as Effect.
OK, so if we utilize effort capability, you'll be noticing that here we also have an effect Maxo here.
OK, so if you don't to the first case when we want to implement the mux out of this slice so we can
actually combine this for.
OK, and considering this three maxus which are being utilized, we actually get six to one.
So that is one of the possibilities.
In a previous case, if utilised, learn.
OK, and then single F seven months you have it two one eight to one mux configuration.
But if you combine all the foodless inside a single slice, you can either have a 16 to one box, which
is a one off the B of implementing a maximum FPGA.
Or the other thing that you can actually implement is the multi input logic equation.
So we need to just find out what how many inputs that we can actually feed.
OK, so here 16 Frankenfood here also we can feed six year olds, we can feed six input here also we
can feed six input.
So in all here we have a twenty four inputs and then we also have a three select total.
We can feed twenty six input logic equation.
OK, so slice.
So if you summarise for a Spartan's six family slice, ok, slice can actually be utilized in the food.
OK, so there are four simple implementation which are possible.
Either you can have two.
In input, logic, accretion.
Logic equation, which can be implemented out of it.
In fact, we can have 16 to one Max.
OK, that is one of the possibility signals as to and that is the third possibility single do this,
too.
And that is the third possibility we have and find a possibility that we have is an implementing 17
and both.
Combination of equation or the logic equation?