So let us try to summarize an FPGA architecture so that you have an AI which controls the functionality
of an AI visibility, mapping the specific needs of an eye opener.
So that will be connected to an object.
Then we have a SILVIS, which are the centralized resources for implementing a logic function, and
then we have a switching matrix.
So they are used to communicate the data between CLB and to implement a complex functionality inside
a CLB.
We have a few slices and then each slice can have a multiple and so forth.
Each slice consists of utilities.
Now there are different kind of slices, so 50 percent of the slices are six, whereas twenty five percent
are slice.
So slices are capable of implementing logic function as well as they also have a full flow for a slice.
And other, on the other hand, have a white multiplexed which can be used to extend the capabilities
of the input as well as you also have a carriage in logic that can be used to speed up an automatic
operation, slice him on the other hand, along with the capabilities that slice and how they have a
specialized luti which can be which can be configured to work as a distributor.
So this is the type of slices.
So 50 percent of the slices of slice X, whereas twenty five percent of slices slice it and then slice
it.
So this also suggests that there is a limitation on the maximum memory that you can generate out of
this.
Right.
So to summarise, this is how a typical architecture looks so green color basically.
And then blue color is an kelby's that we also have a memory controller that are used to control an
external membrane.
Sources other than that, the red color.
We have a dedicated memory which doesn't block Ramogi.
So this is not been implemented from the CLB, but a dedicated memory resources that is available on
an FPGA.
OK, we also have DSP slices to speed up a signal processing application and at the center we have a
clock management system which handle all the clock related operations such as synthesis, generation
of a clock and then changing office and so on and so forth.
We also have breaking point to speed up our PCI to handle PCI operations with the gigabit transfer rate.
So this is how a typical budget look, or if you look at this, all of the resources that are on our
on and FPGA to.
OK, so just to summarize, on the on the periphery, we have an aisle blocks then that is at the center
we have a clock management, which basically this group of clock to all the resources of an FPGA.
We also have a -- point to handle transactions, memory dedicated memory controller, two to communicate
with then.
Memory devices such as.
Then we also have a CLB Sushmita with the then we have a Sylves which are shown within a blue color
over here, small rectangular boxes, the dedicated memory available on an FPGA we just have.
So this memory is not being implemented from the slices, but a dedicated memory resources which even
though are limited but still can be utilized independently.
OK, the saffron color either slices which are used to boost up the signal processing application and
then we have an buffer's.
OK, so this is how a typical FPGA di look.
And then you already have no idea about what is inside and every company right now, we are ready to
proceed with understanding and.