We completed our simulation, the next step that we have is an ideal analysis right now here.
The most important option that we frequently utilize is the schematic, right?
So you'll be finding with an ideal analysis, we have a schematic.
And then after we perform a synthesis, we also have a schematic and after implementation also, we
have schematic rate.
So two of the schematics, which are very, very useful, is the schematic that you get with an ideal
analysis and the schematic that you get with the synthesis rate.
So with an ideal analysis, you get the schematic that you understand, right?
And when you consider the synthesis now here, your steel goal is transformed into an SPG chemical state.
Finally, we have an FPGA architecture, so we need to convert a steel cooled into something that are
FPGA, Mr Right.
So we have a set of primitives available for each FPGA device.
So synthesis transform our code into the set of primitives consisting of a sale sign in it.
Okay?
And that could be understood by and Fiji, right?
So synthesis will represent your transformation of your input into the FPGA, these primitives.
Right.
Whereas schematic a represent the basic symbols that we used in a digital electronic to represent you,
right?
For example, here you have an simple-minded we already know the symbol for an aggregate, so this will
be converting an entire system to a simple blank.
So if you just go to an Italian analysis and if you analyze the schematic.
So here you'll be finding the symbols that you already use in a digital electronics.
OK, so here you could see this is the familiar symbol for angry, OK, and then you have this two empty
and B and then we have a white right.
So ideal analysis basically give you the first view of the actual court so you could just go through
and analyze whether you are getting the schematic as expected.
Right?
The next step is the synthesis, right?
No synthesis, this formula is still good to something that are journalistic.
Right.
So we just need to perform a synthesis and we'll be using the default option or we're here, right?
Sonar synthesis is completed, right, so will just be opening up synthesise design, so you have an
option to open the synthesized design from here, or we could just go ahead and click on this open to
this is to say this will automatically open synthesis design right now.
Here you could see the default view that we get is the package, right?
So there's all reprising the pen that you have, right?
So we would just work on any wall of things and then you could say no, that there's been no eat well
and side, and it also specify the bank well, we do not worry much about this.
The second view that you get is the device rate.
So here you can see AI logic.
So this is an FPGA time that we have, right, so we haven't yet specified the constraint.
OK, and then after that, clearly we believe we do see that logic has been added into an entirely computer.
Right.
So these are the two default something which is very important in this, right?
So you, by default, get an iReport view where you go to a skill level.
You could clearly see all the food that you have in your design to really represent an input.
And why represented that?
All right?
If you do not able to find this view, you could just go to a layout and select a nice blend, right?
So this will automatically bring a package device.
Right?
Now here you have a package to package been replacing the three footer bin that you have one in a 3G
where you want to connect this input.
Right.
So since this tool represents an input, will be connecting this to a switch and to the elite, right?
So you could just go ahead.
And look for the specific master, it's justified.
So here I am utilizing disabled six seven one zero, so I just search for a monster.
It's justified.
OK?
And most probably will be finding next to see file is available on data, right?
You can just go in and then you have a search.
As far as searches, you have this unique number, right?
So for Switch zero, you have 50 and be 50 to this present in the package.
So we'll just go ahead.
And here we will specify 50 and 50.
So some of the peripheral names are also mentioned on, so this is the development that you are utilizing.
OK, so here you could see we have our full switches, right and the few ladies over here.
So just below the switch, OK, you could find out that this is a switch number three and the unique
package bin to which it is connectivity.
So 16, the blue 13, 15 and 50, right?
So this represent the S.V. of finding the pin number right.
So not although they will have this VIN number been mentioned, but variable they have mentioned.
You could always utilize the gourmets.
You go ahead and look for a master file.
They will be finding all the peripheral information, but for a simple Typekit like switch leads the
push button so you could always look for the unique number, right?
And just next to the Pettiford in the back to here, you would see we have an Elite Three, which is
connected to the right.
So this elite is connected to pin number.
So that is what we will be specifying over here and see that the default level which is chosen for a
new standard, you just change it, right?
So I'll be changing it to the max intensity that is and we see most territory.
So this basically represents that we are considering applying three point table.
Right?
So this completes.
Process of adding a continuing rate.
So in our absolute school, we have Eby I like and we are able to connect it to the FPGA instead is
chief of 2015.
And so this is what is mean by a constrained flight.
So to create a constraint.
After you specify design and scalable, you just need to see your less control less and.
Given into a fight, so we'll just be naming this has stop.
We'll get now if you go to a small step.
So with a scene?
OK, hold it.
Now you have a talk to do so if you just open.
You could say no, that are.
All the codes are connected to the respective rates of this complete AH, synthesis.
OK, so synthesis basically transform your article code to the FPGA to make it data that could be understood
from an necklace also.
Right.
So you have a series of nets and then you have a sense, right?
So selling through the Input-Output buffer and the anchor trade, so which is implemented with the help
of it and you?
Right?
So it is basically as an internal substrate.
The next important thing to realize is the schematic.
So let me just go ahead and try to find out the schematic.
So now if you analyze this schematic, which is available in a synthesis, you could clearly see this
is different than what we've seen in our analysis, right?
So this is how your school will be transformed into something that you are if you are listening right
to L.A., I don't know mental block that you have in Fiji and which I utilize implement a logical extraction,
right?
And then you have a series of buffer.
Right.
So this complete the synthesis, the process of synthesis.
And now remember, before performing and implementation, we must specify the constraint side so that
they are required to choose the specific side on Fiji.
They are logic will be placed.