So let us try to summarize an entire design for Rachel.
First step is to specify our design, right?
And we have a two types of design entries over here.
So it could either be text base, OK, or it could be a schematic straight.
So these are the two ways by which you could perform the design entry.
So in the text base, you could either specify of your steel source code or very lock source code.
OK, and then we have a system very lock source code.
So these are the three popular language that we frequently replace.
Then in the schematic based design method, here we use our block design, right?
So as we progress towards an eyepiece, we will be understanding more on this right.
So once I source been specified and along with this, we completed the behavior that we are intended.
OK?
The next step is to check whether it is operating functionally correct date and how we verify it.
We basically apply a stimulus to an input and observe an output crate, and that is done by the step
two, which is a behavioral simulation, right?
So behavioral simulation could be divided into three categories.
So it will be a pre synthesis behavioral simulation.
So let's assume you haven't performed synthesis as well as implementation so that represent the first
simulation where we just apply a stimulus.
OK, and then also the response we are getting on initial core right that that is.
PRISM, this is a behavioral simulation next one that we have is opposing this is behavior simulation
right after we performers and this is the again perform a behavioral simulation because there will be
the differences in the.
So behavioral simulation could be divided into three categories, right?
First is when we haven't performed this synthesis.
OK.
That is where we perform a function of verification.
So just we have performed and implementation of our system will give it the source code.
So behavioral simulation could be divided into three categories, right?
So we haven't performed synthesis yet.
And then we are just checking whether our deal is behaving correctly.
So that is the first behavioral simulation.
The next one is after we performance, and this is we again perform our verification of our system functionality.
That is the second behavioral simulation.
No, there we could also verify whether timings are also correct or not, right?
And the third is when we perform an implementation, right?
So these are the three different kind of behavioral simulation that will be performing great synthesis,
transform our HDL code to something that our FPGA and this generated consist of net sensors also celebrating
the primitives, which are available for a specific device family, right?
Something which we could do to optimize the primitives that have been invoked by default by and we will
do is to utilize the sitting state and these are the optimization strategies.
So common optimization strategies include the number of bugs that you could get both genes that you
could invoke in this.
And the second one that we frequently utilize is the including stay low key when we have a complex surface.
The third one could be whether you want to control the dynamic power distribution.
OK, so adding a clock?
So these are the three popular techniques that we frequently utilize in a sentence is now you would
see that when we specify idea you, so HDL will be transformed to an FPGA primitives.
OK.
So it became mandatory to verify the functionality, whether I device or whether our system still behaves
as expected.
Because when we perform a behavior simulation prior to synthesis, so we consider any still go right
now, still call this transform into a primitives so it becomes mandatory that you even do.
If you do not apply those synthesis strategies, it becomes mandatory that you perform behavioral simulation,
right?
So this is the post synthesis behavioral simulation, and this could be referred as previous synthesis
and present.
This is basically mean that it is also pre implementation, OK?
And the third category is the post implementation.
OK.
Then once we have our design now here, we need to specify before proceeding for an implementation,
we need to specify a constraint, right?
That is mandatory.
So we'll be choosing, depending on the pool that we have in our source code, will be connecting it
to the specific peripheral that we want to connect them.
OK, and that is mainly data, because utilizing them are we?
Why do we decide where the logic should be placed in an FPGA, right?
So here constraint should be added monetarily.
Once that is done, we will proceed to an implementation date.
This will automatically do the placement.
So as soon as we specify a constraint that we would all automatically choose the most suitable site,
depending on the pins that we specify right here.
We could also adopt some of the strategies if you are designing required certain specific constraint.
OK, so these include the area constrain or timing, constrain or power constraint.
OK, so we could adopt the optimization techniques OK by adopting the implementation strategies while
we are performing an implementation.
So this could be done by going into a setting of an implementation and choosing the specific optimization
strategy.
Right.
So once your design is implemented again, you need to perform a behavioral simulation right to this
basically representing our third behavioral simulation, which is post implementation behavior simulation.
So once the implementation is done, the next step is to generate the R programming.
Quite OK.
And then you basically open that hardware manager to program and FPGA to the generated big fight.
So after this, five steps are completed in a case.
If you are required to debug a design, then we basically add the debugging technique.
So this includes I'll NPI, right?
So this is an entire flu that we follow for developing an application on an FPGA, right?
So we'll just be summarizing here one by one.
So the first step is the design entry design entry could be take space or it could also be the schematic
there straight to one to specify a design with an ideal goal.
We will be performing the behavioral simulation.
So this represents a step, too.
Again, this is basically police into behavior and simulation, then the third step is to perform synthesis,
right?
So this will basically transform your HDL to the primitive so give up and produce that is available
for the specific device family, which you have chosen by creating a project right here.
Also, you could adopt certain optimization if you required to if you have a specific constraints,
OK, so you could adopt an optimization technique.
So these are usually the resource optimization, right?
Then as you complete your synthesis here.
After this, we need to perform post synthesis behavioral.
Simulation, right?
So this completed step four, so once it matches to the expected returns, it once it gives us an unexpected
result, the next step is to perform an implementation.
Now we could adopt here also and optimization strategies.
OK.
If you want or you will just stick to the default optimization strategies which are available, right?
So once you perform an implementation, you basically need to perform forced implementation.
Behavioral simulation.
So once you complete this, you go and change the bitstream.
OK, so this should be followed by degeneration of a bitstream.
Right?
And then we could just program high rate.
And if you are not getting an expected return, we proceed with head debugging, right?
So we check for an error.
And again, we go ahead and modify our code right.
So basically, we will again be jumping from a debugging step to any deal.
Right.
So here will again be performing a modification.
A game will be following an interest rate.
So this is how we will be developing an application on an FPGA.