So let us try to understand what are the different options that we get with the synthesis setting as
well as in the next really will be understanding the different strategies that we get with an implementation
starting before proceeding to understand the complete design, right?
So to go to a synthesis setting.
You just need to go either sitting over here or sitting over here.
OK, but the option would work in a similar fashion.
You'd just be clicking on setting and we are targeting a synthesis state.
So when you go to synthesis now, you could see that you have a series of strategies related to the
synthesis, right?
So you could perform any optimization.
You could also optimize optimize store performance.
OK, and then you also have a runtime optimization, right?
So there's a series of strategies which can be adopted.
The more information on this could be easily found out on the reference manual that we have for and
we like, right?
Some of the common strategies that we frequently utilize is the gated clock conversion rate.
So you could see the dynamic power by enabling the delegated lock conversion rate to what that means
is listen to you.
Your device consists of many such blocks in your system, right?
So what this means is we are basically performing an ending between clock and the gating signal.
And then when the gating signal is high, only at that instance, we are sending the clock signal to
both the registered or higher rate.
So these are simple d flip flop that we have and what we are doing is the clock that is going to boot.
The register is and deal with the gating rate.
So we have a gate in between the locking it out, right?
So this is not a good practice when we consider an FPGA because FPGA atop the specific lines for delivering
the clock signal from a plot of three.
So if you have many such blocks at present and you are designed to looking into each and every block
and then a window and gate is a bit difficult task, right?
And it is also a time consuming.
Instead, what you could do is so you could just enable a locking gated to blocking conversion and that
will automatically handle this scenario, right?
So first, we'll just be understanding how this design will be transformed to a primitive state for
this to register.
So when we perform a synthesis, this will be giving us NAFTA, OK, which is basically deeply flawed.
OK?
With the positive edge of the area, there do exist a different kind of a deeply flawed, severe utilizing
FTA, which is deeply flawed with blocking able and synchronous research.
Right.
So we have put the primitives been applied over here and for an engaged will be utilizing LTE to right
because we have simple two inputs, so we are utilizing energy to create.
Now we have many such block present in our design, right, and foreign input and output.
We basically I and I both and so here you could see to I booked an ad.
So we have presence of many such blocks in our design.
Now, once we enable, if you go to a setting and once we enable this gated conversion.
OK.
If you just select and on over here, OK, in that case, what will happen is now the easiest ideas.
Now we want to apply the clock whenever gate is high, right?
So we could connect this gate signal to a clock enable.
And that is the strategy.
What is adopted, one to enable a greater clock conversion rate.
So as soon as you enable a beautiful conversion, you could clearly see the gate signal OK is being
applied to the clock enable of FDI.
OK, so it has been acting as the clock enabled for both the register and thereby we are preventing
the presence of any logical gate.
OK, between the clock rate and that basically seems a good amount of power.
Right.
So this is the strategy that is helping us easily optimize our entire system, right?
So we do not need to look for each and every part of our design for the presence of this specific block,
OK?
We could just enable the gated block conversion and then we able to get an optimized circuit rate.
So more of this could be more similar.
Example could be if you have a multiple gate.
OK, bridging between the part of your clock in that is also one to enable the gateway clock and religion
you could see.
OK, they'll be able to automatically choose what is the signal that should be out at two o'clock?
Enable and clock is kept on the single independent clock light.
So here you would see.
We basically want to perform or we want to send the clock to the register only when gate one and gate
to boot out to, right.
So in this case, the good strategy will be to add a lot.
OK, where we feed gate one and two and then feed this to the clock, enable rate and clipping clock
on the separate lock lane.
OK, and then feeding that to a clock.
Right.
So this you automatically get if you enable the gate clock.
And much like the next strategy that we have, all that we frequently uses right to bug the number of
clock before that you have in your device, right?
So we have a limited amount of count which are present in each and every device.
OK, so twelve is the maximum count that we have in the pool that we have selected over here, right?
So if you want to keep it about, you have a level four and either subsystem.
OK, so let's assume you are designing one offers up system and then someone else is designing another
subsystem, right?
So you are restricted to utilize the limited number of PUBG, then that could be controlled over here.
Right to good specify according to a requirement above you that are allowed and then your entire design
will automatically be implemented considering the account that you specify.
Right.
The next one that we frequently utilizes FSM right to as we build up our control, but so we frequently
use the complex FSM OK to implement our control by.
So in that case, there is a team you want to control, though, including used for the implementation
of benefits.
And Rachel, if you want to have a simple circuit, the good strategy will be to use and when encoding.
But if you want and that also give us a good amount of performance, right?
But that to consume a more area that's compared to the other encoding technique, right to, for example,
beagley including will consume a lesser amount of memory as compared to our including excel in OneNote
and goodI if you just look to how the different technique encode the street.
So if you assume that we have a five state, so each bit will be saying OK for a student, one heart
encoding.
So since we have a five students, we require Typekit variable rate.
So this leads to very simple logic.
But then we are going to mean more right?
And this logic is a bit faster because we do not need to perform an decoding operation over here, right?
If you consider it a binary code and the Greek or both will consume less amount of money.
But since we need to add a decoding logic, they are a bit slower.
So depending on the requirement that you are targeting, you could choose which type of including to
be adopted for your control by deficit, right?
And that could be done by utilizing.
The option that you get in a synthesis setting and which is FSM extraction.
So these are some of the frequent techniques that we utilize in our design.
Right.
So the more discussion on this of more understanding of this could be done easily by going through a
reference manual.
OK.
But some of the strategy, which give us more insight into how the synthesis setting could be adopted.
So we have discovered some of the fundamental thing that we frequently do just to get an understanding
of how synthesis setting would be helpful in optimizing the certain blocks present in our design.