1) One Hot Encoding
In the one-hot encoding (OHE) only one bit of the state variable is “1” or “hot” for any given state. All other state bits are zero. Therefore, one flip-flop (register) is used for every state in the machine i.e. n states uses n flip-flops. State decoding is simplified, since the state bits themselves can be used directly to indicate whether the machine is in a particular state. Often times, no state decoding is necessary, and state encoding can only require the OR-ing of state bits.
One-hot encoding (OHE) is better suited for use with the fan-in limited and flip-flop-rich architectures of the higher gate count filed-programmable gate arrays (FPGAs), such as offered by Xilinx, Actel, and others. OHE maps very easily in these architectures.Bi
2) Binary / Sequential Encoding
In this technique, the states are assigned in binary sequence where the states are numbered starting from binary 0 and up. Binary encoding uses fewer flip-flops/registers than one-hot encoding. For example, binary encoding requires only seven (flip-flops) registers to implement a 100-state machine while a one-hot encoding needs 100 flip-flops. Binary encoding uses the minimum number of state variables (flip-flops) to encode a machine since the flip-flops are maximally utilized. As a result, it generally increases the amount of combinatorial logic because more combinatorial logic is required to decode each state.
Binary encoding is implemented more efficiently when using PLAs and CPLDs.
3) Gray Encoding
Gray code assignment is a state assignment in which consecutive states codes only differ by one bit (adjacent). In other words, only one flip-flop changes at a time when changing consecutive states. Gray code uses the same number of register (flip-flops) as the binary coding technique and the decoding logic can also be as complex if not more. Therefore, gray code assignment is also ideal for PLA and CPLD applications since they have wide gates and a large amount of combinatorial logic per register. Gray code is highly recommended in PLA and CPLD applications when designing for low power requirement.