So now let's try to perform a simulation.
So for that, we'll be adding with this feature to select the simulation source, go ahead and click
on this plus button and create a simulation.
So click OK, create play.
And we'll just be naming this as RAM, right?
And we'll finish notice which schools do not consist of any input and output pool.
So we'll just be clicking.
OK, great.
Again, we need to go to a curriculum page where we have this Panchkula relating to will just be copying
an entire quote.
And then adding it into the TV, which has been added over here, right, so the simulation this will
be finding along with the design code, you also have a test which will just open.
It will delete everything, the complete that has been created by default and then flag the code that
we copied from the cubicle.
Right.
So as soon as you do this, you'll be finding the RAV4, which represent our designed to automatically
become a daughter model and drama school TV, which is our testing school and its name will serve as
the pattern.
OK, if this happens, we are ready to proceed.
Great.
Then we proceed to the next step where we click run simulation and behavioural simulation.
OK, so the code that we have written it just in reading a few random number, applying it onto a random
memory and taking the CMB down.
So if you do, this time plays a code.
What we are doing is, of course, we are performing a right operation, so here you could see right
signal is high.
OK.
And then we are making raids.
So here we are basically reading the data and I'll put in a village also high in that specific instance.
So the Leader API ranking is zero five.
Right?
And from this block onwards, we are reading the data and you see see you fly the data that we have
written.
Right.
So this completes the functional verification of OK, so it is behaving correctly, then the next step
is to perform a synthesis, right?
So in an ideal analysis, you could analyze the component which have been invoked while you I still
could.
We just go ahead and analyze the schematic, analyze the schematic for an ideal.
OK, so you can clearly see the idea of them being involved in the series of raids this too far.
Reading back to Detroit, we utilize it for that reason, we have an IPL regular here, right?
So this is the schematic, then we will be proceeding for.
Performing synthesis, so we'll just go and click on grand synthesis.
So as soon as you are saying this, this is complete, it will just go away and when a synthesis did
say.
OK, and then we will just be performing a.
Remember that before proceeding for an implementation.
We need to specify the port they we want to connect our.
I that we have in our design, right, so what we're going to do is we'll just go to a small step,
OK, in a screen folder, we'll just be right clicking and outsource.
So this will give us an option to add a new constraint.
OK, we'll just be naming this stop and we'll hit right now if you just go away.
And then they stopped or next.
OK, who year?
We do not have anything so inaccurate can be.
The third thing which is mentioned is the cancer gene.
So we'll just be copying this and we'll be adding it all right to this complete on.
And then what are we going to do this so to perform about poverty analysis?
We'll just reload our synthesis to say, OK, and what we are planning here is we will be adopting one
of an implementation strategy.
So you already know that synthesis will transform our actual goal into the FPGA primitives, right?
So as soon as you perform a synthesis now, as soon as we are constrained, you could see that synthesis
out of the right.
So good idea would be that you again perform a synthesis one more time with an updated Consti so that
when we perform and follow me coming there, it could take the related data for computing.
The dynamic power that you are consuming will just be performing a synthesis one more time off the addition
of constraint.
So our synthesis is completed again, they now will go ahead and will try to measure the power.
So you do see you have an option as well, put power over here.
So we'll just be going ahead and report power.
And they're the only important parameter that you want to analyze is.
Does switching and switching.
You could see you have a gene clock, so here you should have a valid.
Leading site, so here we are considering the nanosecond clock, and we're just here to right, so this
will automatically compute the bomb before it's so innocent.
Is this OK?
You could see the clock is consuming 50 percent of of power, whereas I are consuming 38 percent of
total power.
What are you going to do?
It will just be keeping the snapshot of this because as we adopt an implementation strategy, specifically
an optimization strategy, we could easily compare the difference rate.
So once you complete the synthesis, the next step now you already know that your design has been transformed
to something that you understand, which is different than in the good.
That will always be the go around simulation and at least perform a functional simulation.
So that is what we to do.
And this will take the same test bench.
So we do not need to write the different code for this right and will again be observing whether we
are getting the same result or not.
Right, so.
Just be going ahead and then we will be analyzing.
So 05 here and then here.
So here we are, getting zero five affinity, right, so this is also matching with the heat that we
are getting in the previous state.
And what are we going to do next?
So we will just be closing this simulation Typekit.
So usually what happens is if your data is not matching in the case of when you perform a synthesis,
so basically you try to delete your stimulus application for you.
Nanosecond, so usually one nanosecond is the time you have for the global reset, right?
So what you going to do is you do not apply any stimulus for first nanosecond and after a nanosecond,
you start applying the stimulus that will in most cases, correct if you are getting any mismatch right.
So since this is completed, we already specify a constraint.
We're here.
OK, so the next step is to perform an implementation.
So depending on the food that we specify a specific location on an FPGA dice choosing where ideologic
will replace OK, and that strongly depend on the boots that we specify in a constrained play, right,
so will allow the implementation to complete.
OK.
And the next.
So now watching this is complete, the next step is to perform an implementation.
So implementation will basically.
Choose the specific location on an FPGA type where I will be placing ideologic right now, here are
a nice to optimize our design for our requirements.
So here we want to reduce our dynamic power, right?
And that could be done easily by utilizing one of an implementation strategy, right?
So we'll go to the setting before performing an implementation.
And then in an implementation, you could actually see that you have an option to opt the power, right?
So we'll just be taking that option and then we'll be proceed.
OK, so here you have power up, design will just be enabling this will click apply and then hit.
So with this modification will be going to perform an implementation, right?
Now here we have adopted one of an implementation strategy.
So this will modify our design, such as to meet the requirement that we specify.
Hence, it becomes mandatory that we perform a kind of functional simulation after the implementation
is complete.
Right.
Again, implementation.
Choose this specific location on an average day, depending on the bent that you have specified.
So specifying a constraint before performing an implementation fee is a very crucial.
So our implementation is completed.
Now what we're going to do is we will be going to open implementation design.
OK.
And here we have a report, our optional.
So in the previous case, you could clearly see the power that we are consuming is 53 percent with the
clock and with an eye, we are getting 38 percent right.
So it will go away and we already adopted the public of strategy for our design.
Just be reporting a power after an implementation rate, so let it just go away again.
Only thing that you need to check is whether constraint clock is correctly specified with the Respect
specification, right?
So here also we have a clock of 10 nanosecond and now you could see that we able to reduce the dynamic
locking.
OK.
Two, forty three percent rate.
So the power up helps to reduce the dynamic sucking dynamic.
Power dissipation at least up to 30 percent.
So that is the maximum range that we get.
But with this simple modification, you could clearly see that we will to reduce the dynamic locking.
In fact, aisle utilization has also increased.
So.
But you could clearly see that with an implementation strategies, you could control the dynamic locking.
In fact, this is a very simple example.
We won't be able to found of the much difference between good reading.
But as you build up a complex example, consuming a lot of resources and a good amount of power.
So there this kind of strategies are very useful so that this modification and implementation in Texas
will will again go ahead.
Tour and simulation are you able to see these options are also enabled, right?
So will just be performing the implementation functional simulation, right?
So this will be the post implementation functional simulation.
Again, we do not require to specify, and it has been the theme that quote could be used for verification
here.
Odds, right?
Yes, go ahead.
And you could clearly see 05 E.F. and then 05.
Right.
So we are receiving the same data and we are speaking right.
So we completely delay implementation.
Also last step is to perform generation of a stream, so we'll just click on indeed, midstream.
Okay.
So this will automatically create a big fight for us, which will be utilized for our programming on
FPGA.
And then we could either debug our design or we could verify the operation of our system on two and
Heidi, right?
So I presume initially successful.
You just go ahead and click on open hardware manager.
OK, then we just need to click on open target or to.
So this will automatically show the world that you have connected to your PC.
Then you just need to program next page.
Right?
So this completes an entire process, OK, that we follow for the implementation of the system on an
SPG, right?
So we specify the source, 60W text based source, or it could be a schematic based source.
OK, then we perform the functional simulation.
OK, then we perform a synthesis implementation and finally generating a bitstream which would be used
to program an FPGA.