This will automatically add a small school, which is named as an operator in the design, so we'll
just be exploring the container off and hopping right?
Now, if you explore the first part, right, so our usual pool is divided into three parts.
We have a library now.
We will be working with the standard and this good logic and this is defined in that standard and the
school logic are just for one one six four.
Right.
So this two state means are mandatory rated.
This will include all the necessary files which are required for us to work with the standard logic
states then, since they have a size of single batch.
So it will be standard on discovery logic, right?
And the direction will be erroneous.
NC, which which represented our output direction, will be output and size will again be single right
now.
In a case of the data flow modeling say we have a set of incognita which are now utilized and the way
you assign the values to an output signal signals by using the signal assignment right?
In this case, you could clearly see that if you observe the net right.
So these are great.
Gives us some information, right?
And did that indeed give us carry Grace, who will be proceeding to declare some might, so some is
represented with s in our court, right?
Then we use a signal assignment operator and then we act e OK.
The logic gate that we require is an X.
All right, so we'll just turn right.
This is how the boy so argued is represented in the right.
They inquire Kerry E and B right now.
Remember this case insensitive do so we could just use and in a lowercase.
All right, it doesn't affect the state.
So this completes the quote.
Now, when you add a multiple stupid in the morning, say to the RFQ as on good and see me that basically
mean for each book.
We have an independent hardware implementation and to verify that we just see that right.
Go back to a wider and then in an ideal analysis, do you have a schematic?
Right?
So we go ahead and click on the schematic.
So if you observe the schematic, so we have an independent hardware for a caddy, which is A9G, right?
And we also have an independent hardware for some, right, which is an example.
So this basically means both the patient will be evaluated in that balance, right?
Now purified the functionality of an outfit.
We go to this simulation, OK, and we'll just be clicking on run simulation, right?
So here we haven't added the test bench rates of test benches, the cool which Genndy, though random
stimulus for us and apply to our duty.
And we could just analyze the response so far.
Right.
But we haven't decided the test bench fully yet, so we need to manually apply the stimulus to the input.
And then we need to observe the response at an output rate.
So as you pull this further, we'll be discussing how we add a test, right?
So we go ahead and click on run simulation and we'll be selecting run behavioral simulation.
So once your simulation window opens up, you'll be finding you have a list of all the pools which are
present in your design.
So we have to input and be and some N.K. basal while the input and output ports are present in our design.
Now we go ahead and apply the random stimulus for any rate, and the easiest method to apply a stimulus
is by utilizing force clock rate.
So we select input directly and then which will slow, right?
The only thing that we want to do is to vary the pin.
Looking for an independent input will be choosing a different period, right?
So here the parade is 100 nanoseconds, so we'll keep as it is when we select the right click first
clock.
OK, here what we want to do is the period that will be choosing is 300 nanoseconds, right?
So this will be our strategy when we have multiple inputs, OK?
And if you want to generate an independent signal, right, so click OK and then we'll be executing
our code four thousand nanosecond.
So here you have an option to execute it, right?
So once you execute, you just click on Zoom, OK, and then you'll be observing the response so far.
Right?
So when EMV, both the inputs are high, so carry should be one and some should be zero, then one off
an input is high.
In that case, some should be high and Katie should be right.
So you could observe we have zero.
Some is that at zero and then we have one zero over here, right?
Still, some is high and carries it right down when booting zero, that is.
And people are zero, something that he should also be.
They do this decrees that are half-an-hour is working correctly.
Right, so this is how we utilize the signals.
I'm an operator who write the code in need have a little more state.
Now the key point to remember here is if you observe the nets, which are present in our design, right?
So we have this as one off on it, which is present in our design.
This is a design that we have in our design.
Similarly, this one is the net that we have in our design.
This one, this one and this one.
So if you observe this net is defined with the near miss, this net is defined, which means see this
net is defined.
OK, with me, this net is also defined, right?
So this net is also defined.
And in fact, this two nets are all this would be finite.
So you could see that all the nets which are present in our design are defined in an entity, right?
Because in an entity we define S, C and B, right.
So here, since all the nets are defined, we do not require to use any signal in our WHO.
Great.
Now we'll consider the next example where we have presence of some undefined net in and design so that
we also understand how we use the signal and then be more.