The next example that we're going to consider is a flight, and this will be primarily to discuss how
we use the signal enough VW wondering right now if you observe the next which are different or have
some need to sign with the help of the entity, right?
So we'll be finding this natives on this.
It is also totally different since we will be declaring yea, b and C OK.
In an integer.
Similarly, a sense zero will also be declaring an integer, right?
So this note is also defined right.
Then this two are also defined, right?
Similarly, this is also defined and this one is also different, right?
The rest of the notes are undefined in our system, right?
So this net do not have any name attached to it, right?
Or this name is not defined in an entity, right?
Similarly, if you're considered this one right, since this is coming from here.
OK, so this is also an undefined name that we have in our design.
This one is also undefined, right?
Rest of the nets are defined.
So if you calculate that we have this one as the first undefined define in our design.
This one represents the second and define it.
And then this one represented to run the finder, right?
So to define such undefined net right, we use signals, right?
So let's see how we use a signal to define this and implement this system.
Right.
So our system consists of three input E, B and C.
OK, then we have two output summary carrier.
OK, right.
So we'll go ahead.
We will use the C project, which we utilize for development off and hopping, right?
So we'll just be closing our simulation.
We go ahead and select the design to target.
Right, right click.
And then you could add a source from here, or you could just click on this plus button, right?
So this will take us to new source who is out, right?
And here we will be adding the new source.
Let it just name this as folder.
Right click OK and then hit finish.
Now here we have three input groups the each of say a single bit, so we could use comma and declare
all of them went straight.
So e b and then seen rates of this represent three input.
That action is input and say this single bit rate, then we have two output for each of these single
to s see out right.
That addiction will be output.
Write this again.
Have a say a single bit.
OK, now this will automatically create the template for a state.
Now you'll be finding we have a dual source code inside design source.
Right.
So that which we used in the previous example.
And now we plan to work with Solaris.
So whenever you have a multiple source, see that you correctly choose the top movie, so top model
will be chosen depending on which source code you want to use for this specific demonstration.
We plan to work with Falak, right?
So the all the steps that you see on the floor navigate.
So we have a simulation synthesis, implementation and Instagram, and even all of these steps will
be performing will be performed on a module which have this three chip neighbor into it, right?
And that basically represent that that specific source code is the top rate.
Now here we want to work with the collider.
So see that as soon as you add multiple source, you correctly choose your top model right to the source,
which is top model will be the one which will be chosen for all the steps that you perform in that FPGA
design.
Right?
So we'll be right click on the collider and then we will be setting it desktop right now.
All the processes that you see in and you navigate that will be on full, right?
So this is the first thing that we do again.
We want to perform a simulation on the collider only, so we go through simulation sources.
So the heroes who you point to sources are there.
We have incorporated, we have a folder and now we want to perform a simulation on the collider.
So we just right click and set it to a stop, right?
So these are the two necessary thing that you need to do when you have multiple sources present in your
project.
Right now we go to a folder, OK, and will perform the necessary modification.
Right now, the expression for some, right?
So if you go ahead, the first logic gate that you have over here is all right.
So let me just declare this as the one.
Right.
So this is a temporary one.
Then let it just declare the 62 and then this thing right now, doesn't it have a size of single?
So all of these databases of single bit?
So we go ahead and we know that undefined net could be declared with the help of Signal, right?
So we could give our signal.
All of this need to have a single size right.
So have the CMC.
So we go ahead and we add D1 Juanma D2 comma.
So whenever you have a multiple net of, say, single digit code, again use a comma similar to what
we did with a few calls.
Then we define the date.
So standard and whole logic, right?
And to initialize the net, we could just use schooland equals two.
OK, and then we add in a single code zero.
So this will declare three temporary variable of, say, single bit.
OK, then we proceed or implementing the circuit.
Right now, you clearly see D1 is equal to E x RB, right?
So we go ahead and we write divide equals two.
Swaggy equals two will be signal assignment.
Right.
So this will request to e expr be right.
This complete our first block.
Then we have.
So if you can observe design, right?
So this represented A. Do it week was to n right.
So this is the second thing that we will vary will be E and B.
So we completed this to get right next to and that we have is this one.
So if you consider the output of this greatest sum again in Buddhist D1 and C in right, so some is
equals to some is still OK even.
XOR with C in right, so we'll just be adding this expression, so this completes the logic for us.
Then if you can see three three is equals two to one and see right three.
Easy to.
The U.N. had seen this week since last July that we have in our design, is this audit right?
And who's out this carry out Sicario this week equals two three three or did great.
So we go ahead and we add seal.
Right?
So SEAL will be close to.
You do.
OK.
All right, so this completes our entire circuit, right?
So this is how we implement the circuit with our data flow, Morgan State and here we also and discern
how we declared an undefined.
Right.
Now we go ahead.
First, we see you are followed by basic controls, OK?
And then we go ahead and open an ideal schematic.
So that is the first process that we do until we complete our source code.
Right.
So we go to our ideal analysis and we choose schematic.
So this will open up the schematic and this should be matching with the schematic that you have utilized
for implementation of your system method of modeling.
Right.
So some basically have SRB and then finally starting that seed, right?
So if you observe X or B whose output is further XOR with scene, right?
And this gives us some OK as they'll carry out as equals to A and B, so EIB, this is that output.
Similarly, B and C, so here you have your XOR output, right?
And the C that output.
OK, so these are the two I get.
And then finally, they are together to get C.
All right.
So this exactly matches to what you have over here, right?
So we go ahead and try to perform a simulation, right?
So we select run simulation.
We already set our folder as a top model in the simulation source also.
So we click on behavioral simulation, right?
Again, we need to apply a manual stimulus to A, B and C.
And since we haven't written any test bench, right, so we go, Hey, we have a b and C, which are
the input to our design, right?
So we select both clock one and zero will be using a different bit rates.
So far, a b that is a good use would lock one two zero and here we will be using a period of three
hundred nanosecond and four C in.
Get one to zero and let it just choose the period of 509 rates, the ones you set up the clock for all
there, they just go ahead and click on this brown button.
Right now, if you also see when all of the inputs are high and ISO is also high, BS all sciences.
Also, in that case, some incredible should be high.
That is what is happening over here.
If you observe this scenario so easy to these high seas, high rate, so we have too high, so our scouts
should be high, some should be zero, right?
So this is also matching to an expected reserve when we have all of them at zero.
So I wrote something sea out should be easy, right?
So I carry out our storm and carry on, but are working at expected and that is also working as expected.