Now, we already understood how we could add an expression to signal and put, now let's assume you
want to assign an expression to a boat or a signal, depending on certain conditions.
Then in that case, we have a two alternatives rate, so we either we could proceed to use a conditional.
Signal.
Statement did we already discussed?
Or we could proceed with the selected.
Signal.
Street, right?
So you could use them to choose, depending on the differing condition, which expression to be connected
to the port or a signal, right, so they differ in we, they create an ideal schematic, but ultimately
we will be performing a synthesis and then we invoke primitives that will be going on and FPGA, right?
So even though the ideal schematic may be different, for example, conditional signals treatment.
OK, so these include the chain of muxes.
So when you observe the schematic that is a more detailed schematic, then you use a condition signal
steedman.
You'll be finding a kind of muxes.
And that basically suggests that the way in which it operates like this, for example, let's assume
we have like, OK, and then we want to connect it to any.
OK, so he represented one of our input when.
Let us assume select is zero, right?
So this is the case else, we want to connect it to a b rated.
This is the simple statement that we have written now.
In this case, what will happen is as we start evaluating an expression.
So first, we will verify whether conditions evaluate to true right.
Save Select is equal to zero, so this condition will evaluate to true.
In that case will be connecting why to any rate, so whatever value that we have on enabled will be
simply sending it on y and the rest of the expression in this case will not be evaluating, right?
So when we have a conditional signal statement, in that case, we go with the priority.
So the expression which is specified first will be evaluated and if the condition that is specified
evaluates to true y will be immediately assigned to that specific value.
OK.
The the rest of the conditions are simply not evaluated.
Right.
So if selected is not equal to zero, so this condition will fail, then only we check the next condition,
right?
So this is how we perform an evaluation on of a conditional signal statement, right?
Whereas if you're going through the selected signals treatment rate, so we have a different format.
So we started with.
OK, for us, the condition is select.
So we are select is right.
So y will be equals to E.
OK, then we have a value of zero.
OK.
Else it will be simply was to be right in this case, what will happen is to all the treatment will
be evaluated in a bad light, right?
So here if you consider the standard analytical logic typewriter, we have a water level.
So in this case, what will happen is we will be verifying whether our expression is is equal to zero.
If that is the case, if it is equal to zero, we will be connecting it to a rate.
So all the multiple expression will be evaluated in pattern.
So as soon as one of an efficient condition evaluates to true to that value will be a saying, and that
is the only difference that we have, right?
So here we will be getting a parallel kind of an architecture where all the conditions will be evaluated
at the same instance.
OK, so all the expression will be evaluated and the expression which evaluates to true.
So the value of that value will be immediately assigned to the pool, right?
Whereas if you consider the conditional signal assignment or conditional signal statement, in this
case, we start with evaluation of an expression that is specified for.
So if that evaluates to true, we won't be evaluating the rest of the expression, right?
So this is the difference that we have.
And ultimately, what will happen is so this won't be creating any performance difference, right?
This is just the way of specifying an expression in and mutual right.
Ultimately, if you observe the synthesis schematic, right, so the ideal that will be actually going
on to an FPGA will be finding in both the cases, we get the same synthesis schematic, right?
So in both the case, the logic that will be going on to an FPGA will remain the same rate.
The only difference in this to Steedman is the way they evaluate and.