WEBVTT 00:00.060 --> 00:02.430 So now we'll try to implement the simple details. 00:02.900 --> 00:06.550 Right, so the new Bill Clinton stuff would be which is an input data. 00:07.170 --> 00:14.460 OK, so if we correctly so depending on the age that we specified for this love, OK? 00:14.820 --> 00:20.100 And depending on the status of research, we will be generating a different outbreak. 00:20.100 --> 00:25.580 So if we specify the age of the clock as Hlozek. 00:25.620 --> 00:25.920 Right? 00:26.130 --> 00:31.530 So on the positive age of a clock, if we set aside or whatever, we have one in B, which is the data 00:31.530 --> 00:33.450 input will be getting a done deal. 00:33.540 --> 00:33.680 Right. 00:33.690 --> 00:36.900 So this is the typical behavior that we have for difficult, right? 00:37.230 --> 00:39.420 So here we already created a source code. 00:39.460 --> 00:44.000 Now what we want to do is first, we declare all the codes which are present in the difficult rate. 00:44.310 --> 00:47.100 So first, let's just proceed with the synchronously. 00:47.350 --> 00:47.610 Right. 00:47.850 --> 00:48.920 So we are to put. 00:50.250 --> 00:58.110 OK, then first we required Clock, which is the global signal that we have the direction will be input 00:58.830 --> 01:03.060 and our size will be a single bit greater in standard and logic. 01:03.090 --> 01:03.330 Right. 01:03.360 --> 01:09.510 This is how we specify the port with an input direction and a single, precise rate. 01:09.510 --> 01:12.690 So we required one more controlled signal, which is reset, right? 01:13.020 --> 01:16.120 So this will have both sides of a single thing. 01:16.290 --> 01:17.700 Next, we proceed. 01:17.970 --> 01:22.920 And the detail would reduce the rate in standard. 01:22.980 --> 01:28.770 And this could logic because they'd also have a sizeable single bit rate again, after articulation. 01:28.770 --> 01:32.400 We need to add a semicolon since some of the ports are still. 01:33.660 --> 01:36.810 Bending to declare the we're here right and and poll tax. 01:37.260 --> 01:43.200 The last poll that we required is the out, Mr. President, our our proposal direction will be out and 01:43.200 --> 01:44.040 title again. 01:44.040 --> 01:46.350 Be out soon than this good writing right now. 01:46.360 --> 01:47.730 This is the last word. 01:47.730 --> 01:52.880 Our deepest love will happen, so we won't be adding any semicolon after it's declared. 01:53.550 --> 01:58.350 So I take love deeply flawed to stop block research, which are the global controlled signal. 01:58.710 --> 02:02.610 Then we have time to take the alt right, which is the detail. 02:02.760 --> 02:06.760 Let us try to implement that behavior of far different right. 02:06.780 --> 02:11.370 So the first thing that we need to specify is the type of circuits we are implementing. 02:11.610 --> 02:16.590 The sequential circuit and the type of research that we have is the synchronous decision. 02:16.710 --> 02:23.390 So when we are a process, we just need to add a clock, OK, as an argument to a process, then begin 02:23.400 --> 02:24.120 and end. 02:24.600 --> 02:30.710 Now just specifying the clock won't create a company for us in a sequence of seconds. 02:30.720 --> 02:35.580 Right now, Clock can have a positive and negative edge, or it could be level three. 02:35.760 --> 02:42.630 So in most of the cases on an FPGA, we will target to use and trigger right so you could choose which 02:42.630 --> 02:43.860 age to utilize. 02:44.160 --> 02:46.950 Now we proceed utilizing the positive age of Ultron. 02:47.000 --> 02:47.250 Right. 02:47.250 --> 02:53.450 So if raising age, right, so this is how we specify the positive age of a block. 02:53.460 --> 02:59.370 And when you want to specify a negative age group, you just need to bench it falling iterate and the 02:59.370 --> 03:04.620 signal that will behave as the clock vs. named that klt, right? 03:04.620 --> 03:07.710 So that is what you need to specify the right. 03:07.740 --> 03:16.200 So as you add, if you need to end right here, when we add the clock every right, so you do not need 03:16.200 --> 03:23.370 to specify what should be done when I'm clocking, when there's not, that is when we define the behavior 03:23.370 --> 03:29.700 for rising age of a clock we do not need to mention and they they'll be white will automatically handle 03:29.700 --> 03:30.310 that process. 03:30.310 --> 03:37.890 So you just need to mention the blocking every day and you need to end it right now will start implementing 03:37.890 --> 03:39.870 the behavior off our deep right. 03:40.170 --> 03:46.080 So first, we'll be waiting for a clock, which then will be sensing the reset because our reset Typekit 03:46.080 --> 03:47.090 synchronous reset. 03:47.100 --> 03:51.120 So when we see synchronous research, so we wait for the clock to arrive. 03:51.360 --> 03:54.960 And on the clock, we will be sensing the reset, right? 03:55.050 --> 03:59.460 So now we add a reset is let's resume active high day. 03:59.760 --> 04:03.860 So whenever reset is high, we will be resetting our flip-flop rate. 04:03.870 --> 04:08.940 So resetting a flip flop basically means we will be adding a value of zero breaks out. 04:09.170 --> 04:09.390 Right. 04:09.390 --> 04:17.420 So the out will be equal to zero right health and indicate the normal operation of our defense lock. 04:17.430 --> 04:23.280 And in that case, it will be simply quality, whatever value that we have wanted in rate. 04:23.520 --> 04:26.390 So it will be the out device. 04:26.400 --> 04:27.660 So this completes the block. 04:27.900 --> 04:30.790 Now here we have our second if statement, right? 04:30.810 --> 04:32.460 So we need to exaggerate. 04:33.540 --> 04:37.710 So this is one block that we have utilized, and this is the. 04:38.680 --> 04:41.220 Second rate, so this completes the perceived. 04:41.470 --> 04:47.650 Remember, just setting the clock in the process, Block 1B creating a sequential component and then 04:47.650 --> 04:49.420 you specify an edge, right? 04:49.720 --> 04:57.870 So to specify the positive age we use rising each day to specify the following age OK, all the nagaraj, 04:57.880 --> 05:05.590 we just need to add Wally H and in the parenthesis mention the signal which behave as a clock in your 05:06.250 --> 05:06.490 right. 05:06.850 --> 05:08.990 So here it will be, right? 05:09.010 --> 05:13.490 So this is how you specify the positive trigger clock and the negative trigger. 05:14.790 --> 05:20.510 Late today do exist and we off specifying the positive and negative clock. 05:20.560 --> 05:24.040 We will be understanding that also as we progress further. 05:24.070 --> 05:24.340 Right. 05:24.670 --> 05:31.720 So when you define a blocking event by utilizing you construct in that GIS LS is not required. 05:31.720 --> 05:36.420 Okay, equally, you could ignore the behavior in an instant, right? 05:36.430 --> 05:38.200 So that is what we did over here. 05:38.200 --> 05:45.220 So we mentioned the blocking of it, but we have not specified what should be done when we add an A. 05:45.280 --> 05:45.580 Right? 05:45.610 --> 05:52.990 So you could simply ignore an else statement in a case when you are declaring the document Typekit forest 05:52.990 --> 05:56.720 of the cases see that you declare the complete behavior, right? 05:56.740 --> 05:58.240 So that is what we did over here. 05:58.490 --> 06:03.940 So researchers act, you hide out will be zero c out and B simply following the right. 06:03.940 --> 06:09.550 So let's just see a code and try to reload a schematic. 06:09.790 --> 06:16.330 So this will give us an idea the company that has been invoked for the code that we have written. 06:16.330 --> 06:22.170 So we are expecting the D flip flop to be invoked for this code if we go to the schematic. 06:22.250 --> 06:25.930 Now you could see the IPL rec S. OK, so we have a flip flop. 06:26.200 --> 06:32.140 So data input then is connected to the this is correct, then the lock is connected over here and the 06:32.140 --> 06:33.360 clock data is positive. 06:33.970 --> 06:34.290 OK. 06:34.540 --> 06:38.340 And we also have a reset connected to a correct recipient. 06:38.350 --> 06:41.070 Rates output is also connected to see. 06:41.270 --> 06:41.920 OK. 06:42.400 --> 06:48.820 The last four word, which is written on an ideal rate, basically indicate the type of research that 06:48.820 --> 06:50.530 we are utilizing. 06:50.710 --> 06:54.590 So this is why NC are basically asynchronous is great. 06:54.880 --> 06:59.380 So as we modify, our call will also be understanding how we invoke and how synchronous.