library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;


entity top is
    Port ( b : in STD_LOGIC_VECTOR (5 downto 0);
           shift: in std_logic_vector(2 downto 0);
           clk, new_ip : in std_logic;
           y : out STD_LOGIC_VECTOR (5 downto 0);
           done : out std_logic
           );
end top;

architecture Behavioral of top is

signal count : integer range 0 to 8 := 0;

signal temp : std_logic_Vector(5 downto 0) := "000000";

type state_type is (load, sft, new_data);
signal state : state_type := load;

begin
process(clk)
begin
if(rising_edge(clk)) then

case(state) is

when load =>
  temp <= b;
  state <= sft;
  done <= '0';
  
  
when sft =>

if(count < shift) then
   count <= count + 1;
   temp <= temp(0) & temp(5 downto 1);
   state <= sft;
 else
   count <= 0;
   state <= new_data; 
   done <= '1';
end if;


when new_data =>
     
   if(new_ip = '1') then
      state <= load;
    else
      state <= new_data;
   end if;

when others =>
   state <= load;
end case;


end if;
end process;

y <= temp;


end Behavioral;