We discuss test bench for a while when we are discussing about the fundamentals of aviation.
Now we'll spend some time discussing about the things that are specifically important when you write
this.
OK, so this is the money that will be using as a reference for which will be writing the various disciplines
and building up off of it.
OK, so what the school is doing is it takes to input for vector time.
OK, so that basically means it is it will only be working on one entity.
OK, I'll say it and then I'll also I'll say OK, and we have utilized our operator to perform an activity.
And finally we have a result onto the first thing that we do is to include all the libraries that we
have in our design and test.
OK, so this is the code for which we are writing a test which so this becomes Dudi or designing the
test.
OK, so first important thing that you will be doing is you can create a new source if you want.
OK.
Specifically a simulation.
So, so you can just start writing it as in school just after you finish your architecture.
So any behavioral is a point where we have finished our duty so that we can leave some blank spaces
and we can start writing the speech.
So first thing that we always do while we start writing the test is to include all the libraries that
are presented, the design and the test, OK?
So you'll be noticing that those are the two.
Header files or and header libraries are we can see the eight years that we have included for developing
a design.
So without thought much, what we'll do is we'll just copy this to Steve Wynn and we'll just be sitting
with you.
OK, so there may be a scenario that you are working on only to cooperation and standard and logic.
So there may be multiple files or libraries that you require.
OK, so first important thing that you'll always be doing is while you write it as venture code is to
include all the libraries that you have using the duty inside the dustbin.
OK, so this is the first thing that will be doing.
Then we proceed with an entity.
OK, we'll just give a name to an entity that it just name and TV.
It's and then we learn and see that the neme that you give to a this bench should not be matching to
design and testing it.
And usually what we do is, for example, we have used the name for our deal to stop.
So we'll just use stop DB as the name for our test bench.
And again, this becomes once you get that habit of writing tests like this, you can easily recognize
this test in school for a specific model.
OK, the second important point is the entity or the test.
Ventracor do not have any iReports.
So this is the second important point to remember.
OK, in fact what we'll do is we'll just be.
Noting down all the checkpoints that we are discussing, so later on, you will not be finding any problem
in remembering the steps.
So the first point is you.
All the.
Library's.
Preysing.
In the debate, this is the first step.
OK, the second step is to.
Do not.
And any both to dispense.
OK.
And then we proceed with an architecture.
So architecture and the name that will be giving is top DB2, off top TV is OK then will begin and finally
we'll just take.
Our architecture.
OK, so the name that we have in place to now here, since we do not have any in reports, will be declaring
an equal signal of same size with the size that we have for opposing the deal will be finding inside
duty.
We have A B and why three put an open book and we also have a direction and who we need to exactly choose
to type that we have used to do.
So the type should be better and less correct for A and B of size for it and for why it should be vector
of size.
All right.
So we'll prosit and signal we declare between architecture and the connection, we'll just signal A
and B, right.
Then signal do not have any direction, so that underscore vector, then we are stranded on this cold
logic.
It should be of size for bitrate, so three down to zero.
OK.
Then the next step is.
To declare a signal for violence.
OK, so why that vector again?
And three down to see, OK, again, remember that the size and type are exactly equivalent to the size
and type that we have used for an input and output inside.
OK, so here the third check point should be that you use C.
DeLay for input and output.
Pulled equivalent signals.
OK, so whatever signal that you use for input and hope to the issue will have the same data, OK,
and the next step is the signal which represent an input put in a duty should be initialized to someone
here and B, represent or equivalent signal for an important input.
So we'll just be using a variable assignment operator and will be initializing.
OK, so this is multi bit, but so we'll be using a double code that just initialize it to see.
So this is an important step, that is whenever you have declared all the signals for all the input
that you have entitled is a.
Select all the input and signal representing an input put and then initialize them to someone.
So usually we initialize them to zero or it may vary depending on the requirements.
So this completes our fourth step, which is.
Initializing.
Input.
Signal a signal representing.
Input to seed or.
User specific value.
OK, so or any other specific answer, we'll just mention any other specific value.
Now, this is mandated.
You cannot just left and put signals blank.
But again, for an output signal representing our output, they should not be initialized to anyone.
So you keep them as OK.
So this completes our Fewster, then we perform the mapping of a signal.
To deal with this basically signify that we'll be connecting our signal to the respective input around
purported.
In the same day, so we start with an insurgency, so they just start an instance named Stephen.
OK, so this is purely a user defined name.
OK, so to distinguish between the different instances, if you have a multiple instance, so to have
a clear distinction between that, we provide a specific name for that instance.
So here we have used the even as an instance name for the component that we are using.
OK, so.
You'll be noticing that we have that report.
OK, so be an invite, so we'll start and the module name is stop, right.
So here will be just mentioning top automatic language, Gqiba.
And then we want E should be connected to any V should be connected to be and why should be connected
to.
OK, so this is an explicit way of connecting a book.
Now here you will be finding an error because we are using a component without including the component
inside an architecture.
Right.
So including a component is very simple.
OK, so we already know that between an architecture and begin, we can declare three or four things.
So we can either declare the component, we can declare the signal, we can declare enumerated due to.
So you can also declare a memory inventory.
So we just copy from the name of identity or name of our duty.
So from top to and then we'll just copy this.
OK, we'll add a keyword component.
And then we'll just be whatever we have coffee, and since we have started a company, we just changed
our company.
So this is the easiest way to.
I guess you just go ahead, start copying from the name of your entity or you and then capitaland and
finally you are a company.
OK, so this is how you declare a company and then you'll be finding immediately the right.
So no duty.
The signal that the president inside our are connected to the design and one important check here is
you'll be finding that now here we have see.
So for that reason, you'll be finally be able to see on this single source.
So if you just say, well, OK, now you'll be noticing that there will be two suits and the top DB
will automatically become our model and we have the duty as a doctor.
OK.
So when you see that hierarchy, that basically means you have correctly follow all the checkpoint that
you have discussed Tuesday night.
Now, what we'll do is we'll try to understand various views of.
Applying a stimulus to do so, you have an idea how you can generate or stimulate.