16-Bit ALU in VHDL

16 bits ALU means it will process a 16 bit data and provide output of also 16 bits. So in the entity section  r and w are two inputs of 16 bits and f is the out of also 16 bits. d is a selection line of three bit which is required to perform various function on the inputs w and r. So for different value of s different operations are performed on the two inputs like when d="0001"  w and r are passed through an OR gate and an output is generated on f. In the architecture case statement is used in which according to changing value of d different operations are performed on inputs r and w. This is a program of basic ALU which can be further modified according to your application :

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu4 is
    Port ( r : in std_logic_vector(15 downto 0);
           w : in std_logic_vector(15 downto 0);
           d : in std_logic_vector(3 downto 0);
           f : out std_logic_vector(15 downto 0));
end alu4;

architecture alu3 of alu4 is

begin
process(r,w,d)
begin
case d is 
when "0000"=>
f<= w and r;
when "0001"=>
f<=w or r;
 when "0010"=>
f<=w nor r;
  when "0011"=>
f<=w xor r;
 when "0100"=>
f<=w xnor r;
 when "0101"=>
f<=w nand r;
 when "0110"=>
f<=not r;
 when "0111"=>
f<=w + r;
when "1000"=>
f<=r - w;
when "1001"=>
f<=r+"0000000000000001";
when "1010"=>
f<=w-"0000000000000001";
when "1011"=>
f<=r;
when others =>
f<="0000000000000000";
end case;
end process;
end alu3;