BCD Display Design Review

The BCD display is a Binary Coded decimal display and this article will talk through and explain this design and just how it works in detail. Each section below explains a specific design component of the BCD design.

PWM

The PWM design is used to generate a Pulse Width Modulated signal (PWM). For this design the PWM block is used to generate a delayed clock signal so that the users can see the values update on the 7 segment displays.

Interface

Generics

All of the generics are explained below:

bit_depth: Determines the resolution of the duty cycle input.

input_clk: The frequency of the signal ‘clk’.

freq: The frequency of the ‘pwm_out’ signal.

Inputs

All of the inputs are explained below:

dutycycle: Dutycycle of the PWM output signal.

clk: Input clock signal.

enable: Enables the PWM output (active low).

Outputs

All of the outputs are explained below:

pwm_out: The PWM output signal.

Usage

When using the PWM design, the dutycylce can be modified however the frequency is fixed by setting the generic value. The PWM output signal is explain in Figure X below.

COUNTER_1

The counter is used to generate a binary count value, which is updated at the frequency specified by the PWM block.

The binary counter component allows for various configurations and options. The counter configuration used in this design can be found in the images below.

BINARY_BCD

This component of the design takes the binary input and outputs the BCD result. This design uses the shift and adds 3 algorithms to implement the binary to BCD conversions.

The shift and add three algorithm works by shifting to the left the number of bits you have on the input.  Whenever you have a number larger than or equal to 5, you add 3 to that column. See the example below:

MUX_2_1

The mux is designed to toggle between showing the BCD output or the hexadecimal value. It’s a very simple design that looks at the ‘SEL’ input and determines whether the ‘A’ or the ‘in0’ through ‘in3’ are displayed on the ‘out0’ through ‘out3’ outputs.

HEX_7_SEG

The hex to 7 segment display design takes in a 4 bit binary input and outputs the 7 bit output that lights up the 7 segment display.

Interface

Inputs

All of the inputs are explained below:

                hex: The hexadecimal value that is represented on the 7 segment display. The values range from                      0 – F.

Outputs

All of the outputs are explained below:

                seven_seg: This output is connected to a 7 segment display which displays the corresponding                                           hexadecimal value on the input.

BASYS_7_Seg

The BASYS_7_seg design is used to display data on the 7 segment displays located on the BASYS 2 or BASYS 3 FPGA development boards. This IP core takes care of the multiplexing and timing requirements. The user needs to just specify the input clock rate as well as the desired multiplexing frequency. This design can be used or modified to control any 4-digit multiplexed 7 segment display. The schematic symbol / IP core of the BASYS_7_Seg can be found in Figure X.

Interface

Generics

Below the entire configuration options are explained:

                input_clk_freq: This is the frequency value of the input clock in Hz.

refresh_rate: This is the rate at which you want each segment in the display refreshed in Hz. For example, if you set this value to 100 each of the segments in the display will be refreshed 100 times each second.

Inputs

Below all of the inputs are explained:

                seg0: Value displayed on segment 0 of the 7 segment display.

                seg1: Value displayed on segment 1 of the 7 segment display.

                seg2: Value displayed on segment 2 of the 7 segment display.

                seg3: Value displayed on segment 3 of the 7 segment display.

                clk: Input clock.

Outputs

Below all of the outputs are explained:

seg: The out that is displayed on the selected segment, which is determined by which an.

                an: Determines which segment is currently being displayed.

                dp: Turns the decimal point on / off.

Display Format

When displaying values on the 7 segment display it is important to understand which bits relate to which segments on the 7 segment display. Figure X shows representations as to which letters represent which segment on the 7 segment display.

Below you can see a mapping of which bits correspond to which letters on the seg0 through seg3 input ports:

 “GFEDCBA”

Be sure to note that a logical ‘1’ will turn the segment off and logic ‘0’ will turn the segment on. When a common cathode 7 segment display is being used be sure to modify the toggle signal such that the initial value goes from “1000” to “0111”.

In summary:

Common Anode: “1000”

Common Cathode: “0111”