2015.4:
 * Version 12.0 (Rev. 8)
 * Revision change in one or more subcores

2015.3:
 * Version 12.0 (Rev. 7)
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Revision change in one or more subcores

2015.2.1:
 * Version 12.0 (Rev. 6)
 * No changes

2015.2:
 * Version 12.0 (Rev. 6)
 * No changes

2015.1:
 * Version 12.0 (Rev. 6)
 * GUI update, no functional changes. Latency and Feedback Latency restricted when SSET or SINIT are true as well as when respective configurations are Automatic.
 * Addition of Beta support for future devices
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 12.0 (Rev. 5)
 * No changes

2014.4:
 * Version 12.0 (Rev. 5)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal GUI updates, no functional changes.
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf

2014.3:
 * Version 12.0 (Rev. 4)
 * No changes

2014.2:
 * Version 12.0 (Rev. 4)
 * No changes

2014.1:
 * Version 12.0 (Rev. 4)
 * Internal device family name change, no functional changes
 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done
 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)
 * Support for Virtex Ultrascale devices at Pre-Production Status
 * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral sim and post- netlists. VCS version I-2014.03-Beta1 or later is recommended.

2013.4:
 * Version 12.0 (Rev. 3)
 * Tooltips added to GUI
 * Support for Kintex Ultrascale devices at Pre-Production Status

2013.3:
 * Version 12.0 (Rev. 2)
 * Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
 * Internal standardization in source file delivery, does not change behavior
 * Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
 * Added default constraints for out of context flow
 * Added support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators

2013.2:
 * Version 12.0 (Rev. 1)
 * Support for Series 7 devices at Production status
 * Updated clock and bus interface associations for IP Integrator support
 * Removing support for Defense Grade Low Power Artix7

2013.1:
 * Version 12.0
 * Native Vivado Release
 * Changed all port names to upper case
 * There have been no functional changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

(c) Copyright 2002 - 2015 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.

DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.

CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
