# 
# Synthesis run script generated by Vivado
# 

set_param xicom.use_bs_reader 1
set_msg_config -id {HDL 9-1061} -limit 100000
set_msg_config -id {HDL 9-1654} -limit 100000
create_project -in_memory -part xc7z020clg400-2

set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.cache/wt [current_project]
set_property parent.project_path C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property vhdl_version vhdl_2k [current_fileset]
read_vhdl -library xil_defaultlib {
  C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/sources_1/imports/Booth/Signed_to_SLV.vhd
  C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/sources_1/imports/Booth/Hex_to_7_Seg.vhd
  C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/sources_1/imports/Booth/binary_bcd.vhd
  C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/sources_1/imports/Booth/Seg_Display_16.vhd
  C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/sources_1/imports/Booths_Algorithm/smult_1.vhd
  C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/sources_1/imports/Booth/Booth_Top.vhd
}
read_xdc C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/constrs_1/imports/XDC/Arty_Z7_Master.xdc
set_property used_in_implementation false [get_files C:/Arty_Z7_Projects/Booths_Algorithm/Booths_Algorithm.srcs/constrs_1/imports/XDC/Arty_Z7_Master.xdc]

synth_design -top Booth_Top -part xc7z020clg400-2
write_checkpoint -noxdef Booth_Top.dcp
catch { report_utilization -file Booth_Top_utilization_synth.rpt -pb Booth_Top_utilization_synth.pb }
