### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
date_generated | Tue Apr 18 23:33:19 2017 | product_version | Vivado v2015.4 (64-bit)
build_version | 1412921 | os_platform | WIN64
registration_id | 211139803_0_0_561 | tool_flow | Vivado
beta | FALSE | route_design | TRUE
target_family | zynq | target_device | xc7z020
target_package | clg400 | target_speed | -2
random_id | fa2d7df0d966501b95ccc4b479e89299 | project_id | e10943df110c42168b53cb0848ea1fab
project_iteration | 1

user_environment
os_name | Microsoft Windows 7 , 64-bit | os_release | Service Pack 1 (build 7601)
cpu_name | Intel(R) Core(TM) i7-2630QM CPU @ 2.00GHz | cpu_speed | 1995 MHz
total_processors | 1 | system_ram | 6.000 GB

vivado_usage

project_data
srcsetcount=6 | constraintsetcount=1 | designmode=RTL | prproject=false
reconfigpartitioncount=0 | reconfigmodulecount=0 | hdproject=false | partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults | implstrategy=Vivado Implementation Defaults | currentsynthesisrun=synth_1 | currentimplrun=impl_1
totalsynthesisruns=1 | totalimplruns=1 | core_container=false

other_data
guimode=1

unisim_transformation
pre_unisim_transformation
bufg=1 | carry4=103 | fdre=324 | gnd=9
ibuf=10 | lut1=130 | lut2=308 | lut3=39
lut4=22 | lut5=159 | lut6=171 | obuf=24
vcc=6
post_unisim_transformation
bufg=1 | carry4=103 | fdre=324 | gnd=9
ibuf=10 | lut1=130 | lut2=308 | lut3=39
lut4=22 | lut5=159 | lut6=171 | obuf=24
vcc=6

report_utilization
slice_logic
slice_luts_used=664 | slice_luts_fixed=0 | slice_luts_available=53200 | slice_luts_util_percentage=1.25
lut_as_logic_used=664 | lut_as_logic_fixed=0 | lut_as_logic_available=53200 | lut_as_logic_util_percentage=1.25
lut_as_memory_used=0 | lut_as_memory_fixed=0 | lut_as_memory_available=17400 | lut_as_memory_util_percentage=0.00
slice_registers_used=324 | slice_registers_fixed=0 | slice_registers_available=106400 | slice_registers_util_percentage=0.30
register_as_flip_flop_used=324 | register_as_flip_flop_fixed=0 | register_as_flip_flop_available=106400 | register_as_flip_flop_util_percentage=0.30
register_as_latch_used=0 | register_as_latch_fixed=0 | register_as_latch_available=106400 | register_as_latch_util_percentage=0.00
f7_muxes_used=0 | f7_muxes_fixed=0 | f7_muxes_available=26600 | f7_muxes_util_percentage=0.00
f8_muxes_used=0 | f8_muxes_fixed=0 | f8_muxes_available=13300 | f8_muxes_util_percentage=0.00
slice_used=211 | slice_fixed=0 | slice_available=13300 | slice_util_percentage=1.59
slicel_used=127 | slicel_fixed=0 | slicem_used=84 | slicem_fixed=0
lut_as_logic_used=664 | lut_as_logic_fixed=0 | lut_as_logic_available=53200 | lut_as_logic_util_percentage=1.25
using_o5_output_only_used=0 | using_o5_output_only_fixed= | using_o6_output_only_used=530 | using_o6_output_only_fixed=
using_o5_and_o6_used=134 | using_o5_and_o6_fixed= | lut_as_memory_used=0 | lut_as_memory_fixed=0
lut_as_memory_available=17400 | lut_as_memory_util_percentage=0.00 | lut_as_distributed_ram_used=0 | lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=0 | lut_as_shift_register_fixed=0 | lut_flip_flop_pairs_used=724 | lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=53200 | lut_flip_flop_pairs_util_percentage=1.36 | fully_used_lut_ff_pairs_used=223 | fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=60 | lut_ff_pairs_with_unused_lut_fixed= | lut_ff_pairs_with_unused_flip_flop_used=441 | lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=13 | minimum_number_of_registers_lost_to_control_set_restriction_used=44(Lost)
memory
block_ram_tile_used=0 | block_ram_tile_fixed=0 | block_ram_tile_available=140 | block_ram_tile_util_percentage=0.00
ramb36_fifo_used=0 | ramb36_fifo_fixed=0 | ramb36_fifo_available=140 | ramb36_fifo_util_percentage=0.00
ramb18_used=0 | ramb18_fixed=0 | ramb18_available=280 | ramb18_util_percentage=0.00
dsp
dsps_used=0 | dsps_fixed=0 | dsps_available=220 | dsps_util_percentage=0.00
clocking
bufgctrl_used=1 | bufgctrl_fixed=0 | bufgctrl_available=32 | bufgctrl_util_percentage=3.13
bufio_used=0 | bufio_fixed=0 | bufio_available=16 | bufio_util_percentage=0.00
mmcme2_adv_used=0 | mmcme2_adv_fixed=0 | mmcme2_adv_available=4 | mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 | plle2_adv_fixed=0 | plle2_adv_available=4 | plle2_adv_util_percentage=0.00
bufmrce_used=0 | bufmrce_fixed=0 | bufmrce_available=8 | bufmrce_util_percentage=0.00
bufhce_used=0 | bufhce_fixed=0 | bufhce_available=72 | bufhce_util_percentage=0.00
bufr_used=0 | bufr_fixed=0 | bufr_available=16 | bufr_util_percentage=0.00
specific_feature
bscane2_used=0 | bscane2_fixed=0 | bscane2_available=4 | bscane2_util_percentage=0.00
capturee2_used=0 | capturee2_fixed=0 | capturee2_available=1 | capturee2_util_percentage=0.00
dna_port_used=0 | dna_port_fixed=0 | dna_port_available=1 | dna_port_util_percentage=0.00
efuse_usr_used=0 | efuse_usr_fixed=0 | efuse_usr_available=1 | efuse_usr_util_percentage=0.00
frame_ecce2_used=0 | frame_ecce2_fixed=0 | frame_ecce2_available=1 | frame_ecce2_util_percentage=0.00
icape2_used=0 | icape2_fixed=0 | icape2_available=2 | icape2_util_percentage=0.00
startupe2_used=0 | startupe2_fixed=0 | startupe2_available=1 | startupe2_util_percentage=0.00
xadc_used=0 | xadc_fixed=0 | xadc_available=1 | xadc_util_percentage=0.00
primitives
fdre_used=324 | fdre_functional_category=Flop & Latch | lut2_used=308 | lut2_functional_category=LUT
lut6_used=171 | lut6_functional_category=LUT | lut5_used=159 | lut5_functional_category=LUT
carry4_used=103 | carry4_functional_category=CarryLogic | lut1_used=99 | lut1_functional_category=LUT
lut3_used=39 | lut3_functional_category=LUT | obuf_used=24 | obuf_functional_category=IO
lut4_used=22 | lut4_functional_category=LUT | ibuf_used=10 | ibuf_functional_category=IO
bufg_used=1 | bufg_functional_category=Clock
io_standard
lvcmos12=0 | mobile_ddr=0 | lvttl=0 | lvcmos18=0
pci33_3=0 | lvcmos33=1 | diff_sstl15=0 | hstl_i=0
diff_mobile_ddr=0 | hsul_12=0 | lvcmos25=0 | diff_sstl15_r=0
hstl_ii=0 | lvcmos15=0 | hstl_i_18=0 | diff_hsul_12=0
hstl_ii_18=0 | sstl18_i=0 | sstl18_ii=0 | sstl15=0
sstl15_r=0 | sstl135=0 | sstl135_r=0 | lvds_25=0
diff_hstl_i=0 | rsds_25=0 | diff_hstl_ii=0 | tmds_33=0
diff_hstl_i_18=0 | mini_lvds_25=0 | diff_hstl_ii_18=0 | ppds_25=0
diff_sstl18_i=0 | diff_sstl18_ii=0 | diff_sstl135=0 | diff_sstl135_r=0
blvds_25=0

router
usage
lut=664 | ff=324 | bram36=0 | bram18=0
ctrls=13 | dsp=0 | iob=34 | bufg=0
global_clocks=1 | pll=0 | bufr=0 | nets=1535
movable_instances=1275 | pins=7098 | bogomips=0 | high_fanout_nets=0
effort=2 | threads=2 | router_timing_driven=1 | timing_constraints_exist=1
estimated_expansions=924324 | actual_expansions=582299 | router_runtime=45.099000

synthesis
command_line_options
-part=xc7z020clg400-2 | -name=default::[not_specified] | -top=ALU_Top | -include_dirs=default::[not_specified]
-generic=default::[not_specified] | -verilog_define=default::[not_specified] | -constrset=default::[not_specified] | -seu_protect=default::none
-flatten_hierarchy=default::rebuilt | -gated_clock_conversion=default::off | -directive=default::default | -rtl=default::[not_specified]
-link_dcps=default::[not_specified] | -rtl_load_constraints=default::[not_specified] | -bufg=default::12 | -fanout_limit=default::10000
-shreg_min_size=default::3 | -mode=default::default | -fsm_extraction=default::auto | -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto | -cascade_dsp=default::auto | -control_set_opt_threshold=default::auto
usage
elapsed=00:00:46s | memory_peak=624.488MB | memory_gain=434.578MB | hls_ip=0