library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity ALU_2 is
	generic (
		bit_depth			: integer := 8);
	port (
		opcode				: in std_logic_vector(2 downto 0);
		A					: in signed(2 * bit_depth - 1 downto 0);
		B					: in signed(2 * bit_depth - 1 downto 0);
		execute				: in std_logic;
		result				: out signed(2 * bit_depth - 1 downto 0)
		  );
end ALU_2;

architecture behavior of ALU_2 is

signal A_int, B_int     : signed(2 * bit_depth - 1 downto 0);

	begin
	
	A_int <= A;
	B_int <= B;
	
	state_op: process(execute)
			begin
			 if(rising_edge(execute)) then
				case opcode is
					-- output A
					when "000" =>
						result <= A_int;
					-- output B
					when "001" =>
						result <= B_int;
					-- output A+B
					when "010" =>
						result <= A_int+B_int;
					-- output A-B
					when "011" =>
						result <= A_int-B_int;
					-- output 0
					when "100" =>
						result <= (others => '0');
					-- output 1
					when "101" =>
						result <= (others => '1');
					-- error code
					when others =>
						result <= (others => 'X');
				end case;
			end if;
	end process;
end behavior;