-- Signed to SLV
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity Signed_to_SLV is
generic(
	bit_depth		: integer := 12);
port(
	Signed_in		: in signed(bit_depth - 1 downto 0);
	SLV_out			: out std_logic_vector(bit_depth - 1 downto 0);
	neg 			: out std_logic);
end Signed_to_SLV;
	
architecture behavior of Signed_to_SLV is

signal SLV_out_reg	: signed(bit_depth - 1 downto 0) := (others => '0');
signal neg_reg		: std_logic := '0';

begin

neg <= neg_reg;
neg_reg <= '1' when Signed_in < 0 else '0';
SLV_out_reg <= (not Signed_in) + 1 when Signed_in < 0 else Signed_in;
SLV_out <= std_logic_vector(SLV_out_reg);

end behavior;