# 
# Synthesis run script generated by Vivado
# 

set_msg_config -id {HDL 9-1061} -limit 100000
set_msg_config -id {HDL 9-1654} -limit 100000
create_project -in_memory -part xc7a35tcpg236-2

set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir C:/Basys_3_Projects/ALU/ALU.cache/wt [current_project]
set_property parent.project_path C:/Basys_3_Projects/ALU/ALU.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property vhdl_version vhdl_2k [current_fileset]
read_vhdl -library xil_defaultlib {
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/BASYS_7_seg/BASYS_7_seg.vhd
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/imports/Signed_to_SLV/Signed_to_SLV.vhd
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/imports/ALU/Hex_to_7_Seg.vhd
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/imports/ALU/ALU_2.vhd
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/imports/ALU/Seg_Display_16.vhd
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/imports/ALU/binary_bcd.vhd
  C:/Basys_3_Projects/ALU/ALU.srcs/sources_1/imports/imports/ALU/ALU_Top.vhd
}
read_xdc C:/Basys_3_Projects/ALU/ALU.srcs/constrs_1/imports/XDC/Basys3_Master.xdc
set_property used_in_implementation false [get_files C:/Basys_3_Projects/ALU/ALU.srcs/constrs_1/imports/XDC/Basys3_Master.xdc]

synth_design -top ALU_Top -part xc7a35tcpg236-2
write_checkpoint -noxdef ALU_Top.dcp
catch { report_utilization -file ALU_Top_utilization_synth.rpt -pb ALU_Top_utilization_synth.pb }
