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-- IP VLNV: xilinx.com:user:binary_bcd:1.0
-- IP Revision: 2

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY design_1_binary_bcd_0_0 IS
  PORT (
    clk : IN STD_LOGIC;
    reset : IN STD_LOGIC;
    binary_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    bcd0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    bcd1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    bcd2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    bcd3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    bcd4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    bcd5 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    bcd6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
END design_1_binary_bcd_0_0;

ARCHITECTURE design_1_binary_bcd_0_0_arch OF design_1_binary_bcd_0_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_binary_bcd_0_0_arch: ARCHITECTURE IS "yes";

  COMPONENT binary_bcd IS
    GENERIC (
      N : INTEGER
    );
    PORT (
      clk : IN STD_LOGIC;
      reset : IN STD_LOGIC;
      binary_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
      bcd0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      bcd1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      bcd2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      bcd3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      bcd4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      bcd5 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      bcd6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
  END COMPONENT binary_bcd;
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
  ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
  U0 : binary_bcd
    GENERIC MAP (
      N => 16
    )
    PORT MAP (
      clk => clk,
      reset => reset,
      binary_in => binary_in,
      bcd0 => bcd0,
      bcd1 => bcd1,
      bcd2 => bcd2,
      bcd3 => bcd3,
      bcd4 => bcd4,
      bcd5 => bcd5,
      bcd6 => bcd6
    );
END design_1_binary_bcd_0_0_arch;
