--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
--Date        : Sat Apr 22 17:44:53 2017
--Host        : Jordan-HP running 64-bit Service Pack 1  (build 7601)
--Command     : generate_target design_1.bd
--Design      : design_1
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
  port (
    C_or_F : in STD_LOGIC;
    XA1_N : in STD_LOGIC;
    XA1_P : in STD_LOGIC;
    clk : in STD_LOGIC;
    digit_select : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dp : out STD_LOGIC;
    reset : in STD_LOGIC;
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=12,numReposBlks=12,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,synth_mode=Global}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;

architecture STRUCTURE of design_1 is
  component design_1_xadc_wiz_0_0 is
  port (
    di_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    daddr_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    den_in : in STD_LOGIC;
    dwe_in : in STD_LOGIC;
    drdy_out : out STD_LOGIC;
    do_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    dclk_in : in STD_LOGIC;
    reset_in : in STD_LOGIC;
    vp_in : in STD_LOGIC;
    vn_in : in STD_LOGIC;
    vauxp6 : in STD_LOGIC;
    vauxn6 : in STD_LOGIC;
    channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    muxaddr_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    eoc_out : out STD_LOGIC;
    alarm_out : out STD_LOGIC;
    eos_out : out STD_LOGIC;
    busy_out : out STD_LOGIC
  );
  end component design_1_xadc_wiz_0_0;
  component design_1_microblaze_mcs_0_0 is
  port (
    Clk : in STD_LOGIC;
    Reset : in STD_LOGIC;
    GPO1 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    GPO2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    GPO3 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    GPI1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    GPI1_Interrupt : out STD_LOGIC;
    GPI2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    GPI2_Interrupt : out STD_LOGIC
  );
  end component design_1_microblaze_mcs_0_0;
  component design_1_Seg_Display_16_0_0 is
  port (
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    dp : out STD_LOGIC;
    an : out STD_LOGIC_VECTOR ( 7 downto 0 );
    digit_1 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_2 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_3 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_4 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_5 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_6 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_7 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    digit_8 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    clk : in STD_LOGIC
  );
  end component design_1_Seg_Display_16_0_0;
  component design_1_Hex_to_7_Seg_0_0 is
  port (
    seven_seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    hex : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_Hex_to_7_Seg_0_0;
  component design_1_binary_bcd_0_0 is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    binary_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    bcd0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    bcd1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    bcd2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    bcd3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    bcd4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    bcd5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    bcd6 : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_binary_bcd_0_0;
  component design_1_Hex_to_7_Seg_0_1 is
  port (
    seven_seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    hex : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_Hex_to_7_Seg_0_1;
  component design_1_Hex_to_7_Seg_0_2 is
  port (
    seven_seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    hex : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_Hex_to_7_Seg_0_2;
  component design_1_Hex_to_7_Seg_0_3 is
  port (
    seven_seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    hex : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_Hex_to_7_Seg_0_3;
  component design_1_Hex_to_7_Seg_3_0 is
  port (
    seven_seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    hex : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_Hex_to_7_Seg_3_0;
  component design_1_xlconstant_0_0 is
  port (
    dout : out STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  end component design_1_xlconstant_0_0;
  component design_1_xlconstant_0_1 is
  port (
    dout : out STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  end component design_1_xlconstant_0_1;
  component design_1_xlconstant_0_2 is
  port (
    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  end component design_1_xlconstant_0_2;
  signal C_or_F_1 : STD_LOGIC;
  signal Hex_to_7_Seg_0_seven_seg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal Hex_to_7_Seg_1_seven_seg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal Hex_to_7_Seg_2_seven_seg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal Hex_to_7_Seg_3_seven_seg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal Hex_to_7_Seg_4_seven_seg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal Seg_Display_16_0_an : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal Seg_Display_16_0_dp : STD_LOGIC;
  signal Seg_Display_16_0_seg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal XA1_N_1 : STD_LOGIC;
  signal XA1_P_1 : STD_LOGIC;
  signal binary_bcd_0_bcd0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal binary_bcd_0_bcd1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal binary_bcd_0_bcd2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal binary_bcd_0_bcd3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal binary_bcd_0_bcd4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal clk_1 : STD_LOGIC;
  signal microblaze_mcs_0_GPO1 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal microblaze_mcs_0_GPO2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal microblaze_mcs_0_GPO3 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal reset_1 : STD_LOGIC;
  signal xadc_address_dout : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal xadc_enable_dout : STD_LOGIC_VECTOR ( 0 to 0 );
  signal xadc_wiz_0_do_out : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_binary_bcd_0_bcd5_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_binary_bcd_0_bcd6_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_microblaze_mcs_0_GPI1_Interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_microblaze_mcs_0_GPI2_Interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_xadc_wiz_0_alarm_out_UNCONNECTED : STD_LOGIC;
  signal NLW_xadc_wiz_0_busy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_xadc_wiz_0_drdy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_xadc_wiz_0_eoc_out_UNCONNECTED : STD_LOGIC;
  signal NLW_xadc_wiz_0_eos_out_UNCONNECTED : STD_LOGIC;
  signal NLW_xadc_wiz_0_channel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_xadc_wiz_0_muxaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
  C_or_F_1 <= C_or_F;
  XA1_N_1 <= XA1_N;
  XA1_P_1 <= XA1_P;
  clk_1 <= clk;
  digit_select(7 downto 0) <= Seg_Display_16_0_an(7 downto 0);
  dp <= Seg_Display_16_0_dp;
  reset_1 <= reset;
  seg(6 downto 0) <= Seg_Display_16_0_seg(6 downto 0);
Hex_to_7_Seg_0: component design_1_Hex_to_7_Seg_0_0
     port map (
      hex(3 downto 0) => binary_bcd_0_bcd0(3 downto 0),
      seven_seg(6 downto 0) => Hex_to_7_Seg_0_seven_seg(6 downto 0)
    );
Hex_to_7_Seg_1: component design_1_Hex_to_7_Seg_0_1
     port map (
      hex(3 downto 0) => binary_bcd_0_bcd1(3 downto 0),
      seven_seg(6 downto 0) => Hex_to_7_Seg_1_seven_seg(6 downto 0)
    );
Hex_to_7_Seg_2: component design_1_Hex_to_7_Seg_0_2
     port map (
      hex(3 downto 0) => binary_bcd_0_bcd2(3 downto 0),
      seven_seg(6 downto 0) => Hex_to_7_Seg_2_seven_seg(6 downto 0)
    );
Hex_to_7_Seg_3: component design_1_Hex_to_7_Seg_0_3
     port map (
      hex(3 downto 0) => binary_bcd_0_bcd3(3 downto 0),
      seven_seg(6 downto 0) => Hex_to_7_Seg_3_seven_seg(6 downto 0)
    );
Hex_to_7_Seg_4: component design_1_Hex_to_7_Seg_3_0
     port map (
      hex(3 downto 0) => binary_bcd_0_bcd4(3 downto 0),
      seven_seg(6 downto 0) => Hex_to_7_Seg_4_seven_seg(6 downto 0)
    );
Seg_Display_16_0: component design_1_Seg_Display_16_0_0
     port map (
      an(7 downto 0) => Seg_Display_16_0_an(7 downto 0),
      clk => clk_1,
      digit_1(6 downto 0) => microblaze_mcs_0_GPO1(6 downto 0),
      digit_2(6 downto 0) => Hex_to_7_Seg_4_seven_seg(6 downto 0),
      digit_3(6 downto 0) => Hex_to_7_Seg_3_seven_seg(6 downto 0),
      digit_4(6 downto 0) => Hex_to_7_Seg_2_seven_seg(6 downto 0),
      digit_5(6 downto 0) => Hex_to_7_Seg_1_seven_seg(6 downto 0),
      digit_6(6 downto 0) => Hex_to_7_Seg_0_seven_seg(6 downto 0),
      digit_7(6 downto 0) => xlconstant_0_dout(6 downto 0),
      digit_8(6 downto 0) => microblaze_mcs_0_GPO3(6 downto 0),
      dp => Seg_Display_16_0_dp,
      seg(6 downto 0) => Seg_Display_16_0_seg(6 downto 0)
    );
binary_bcd_0: component design_1_binary_bcd_0_0
     port map (
      bcd0(3 downto 0) => binary_bcd_0_bcd0(3 downto 0),
      bcd1(3 downto 0) => binary_bcd_0_bcd1(3 downto 0),
      bcd2(3 downto 0) => binary_bcd_0_bcd2(3 downto 0),
      bcd3(3 downto 0) => binary_bcd_0_bcd3(3 downto 0),
      bcd4(3 downto 0) => binary_bcd_0_bcd4(3 downto 0),
      bcd5(3 downto 0) => NLW_binary_bcd_0_bcd5_UNCONNECTED(3 downto 0),
      bcd6(3 downto 0) => NLW_binary_bcd_0_bcd6_UNCONNECTED(3 downto 0),
      binary_in(15 downto 0) => microblaze_mcs_0_GPO2(15 downto 0),
      clk => clk_1,
      reset => reset_1
    );
microblaze_mcs_0: component design_1_microblaze_mcs_0_0
     port map (
      Clk => clk_1,
      GPI1(15 downto 0) => xadc_wiz_0_do_out(15 downto 0),
      GPI1_Interrupt => NLW_microblaze_mcs_0_GPI1_Interrupt_UNCONNECTED,
      GPI2(0) => C_or_F_1,
      GPI2_Interrupt => NLW_microblaze_mcs_0_GPI2_Interrupt_UNCONNECTED,
      GPO1(6 downto 0) => microblaze_mcs_0_GPO1(6 downto 0),
      GPO2(15 downto 0) => microblaze_mcs_0_GPO2(15 downto 0),
      GPO3(6 downto 0) => microblaze_mcs_0_GPO3(6 downto 0),
      Reset => reset_1
    );
xadc_address: component design_1_xlconstant_0_1
     port map (
      dout(6 downto 0) => xadc_address_dout(6 downto 0)
    );
xadc_enable: component design_1_xlconstant_0_2
     port map (
      dout(0) => xadc_enable_dout(0)
    );
xadc_wiz_0: component design_1_xadc_wiz_0_0
     port map (
      alarm_out => NLW_xadc_wiz_0_alarm_out_UNCONNECTED,
      busy_out => NLW_xadc_wiz_0_busy_out_UNCONNECTED,
      channel_out(4 downto 0) => NLW_xadc_wiz_0_channel_out_UNCONNECTED(4 downto 0),
      daddr_in(6 downto 0) => xadc_address_dout(6 downto 0),
      dclk_in => clk_1,
      den_in => xadc_enable_dout(0),
      di_in(15 downto 0) => B"0000000000000000",
      do_out(15 downto 0) => xadc_wiz_0_do_out(15 downto 0),
      drdy_out => NLW_xadc_wiz_0_drdy_out_UNCONNECTED,
      dwe_in => '0',
      eoc_out => NLW_xadc_wiz_0_eoc_out_UNCONNECTED,
      eos_out => NLW_xadc_wiz_0_eos_out_UNCONNECTED,
      muxaddr_out(4 downto 0) => NLW_xadc_wiz_0_muxaddr_out_UNCONNECTED(4 downto 0),
      reset_in => reset_1,
      vauxn6 => XA1_N_1,
      vauxp6 => XA1_P_1,
      vn_in => '0',
      vp_in => '0'
    );
xlconstant_0: component design_1_xlconstant_0_0
     port map (
      dout(6 downto 0) => xlconstant_0_dout(6 downto 0)
    );
end STRUCTURE;
