-------------------------------------------------------------------------------
-- gpo_module.vhd - Entity and architecture
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
-- Filename:        gpo_module.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              gpo_module.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
--
-- History:
--   goran  2007-12-19    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity GPO_Module is
  
  generic (
    C_USE_GPO    : integer := 1;
    C_GPO_SIZE   : integer range 1 to 32 := 32;
    C_GPO_INIT   : std_logic_vector(31 downto 0) := (others => '0'));
  port (
    Clk        : in  std_logic;
    Reset      : in  boolean;
    GPO_Write  : in  std_logic;
    Write_Data : in  std_logic_vector(31 downto 0);
    GPO        : out std_logic_vector(C_GPO_SIZE-1 downto 0));    
end entity GPO_Module;

architecture IMP of GPO_Module is

  signal gpo_io_i : std_logic_vector(C_GPO_SIZE-1 downto 0);
  
begin  -- architecture IMP

  Use_it : if (C_USE_GPO /= 0) generate

      GPO_DFF : process (Clk) is
      begin  -- process GPO_DFF
        if Clk'event and Clk = '1' then  -- rising clock edge
          if Reset then                  -- synchronous reset (active high)
            gpo_io_i <= C_GPO_INIT(gpo_io_i'range);
          elsif (GPO_Write = '1') then
            gpo_io_i <= Write_Data(gpo_io_i'range);
          end if;
        end if;
      end process GPO_DFF;
      
  end generate Use_it;

  Empty : if (C_USE_GPO = 0) generate
    gpo_io_i <= (others => '0');
  end generate Empty;

  GPO <= gpo_io_i;
end architecture IMP;
