--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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--Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
--Date        : Sat Apr 22 17:44:53 2017
--Host        : Jordan-HP running 64-bit Service Pack 1  (build 7601)
--Command     : generate_target design_1_wrapper.bd
--Design      : design_1_wrapper
--Purpose     : IP block netlist
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
  port (
    C_or_F : in STD_LOGIC;
    XA1_N : in STD_LOGIC;
    XA1_P : in STD_LOGIC;
    clk : in STD_LOGIC;
    digit_select : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dp : out STD_LOGIC;
    reset : in STD_LOGIC;
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 )
  );
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
  component design_1 is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    C_or_F : in STD_LOGIC;
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    dp : out STD_LOGIC;
    digit_select : out STD_LOGIC_VECTOR ( 7 downto 0 );
    XA1_P : in STD_LOGIC;
    XA1_N : in STD_LOGIC
  );
  end component design_1;
begin
design_1_i: component design_1
     port map (
      C_or_F => C_or_F,
      XA1_N => XA1_N,
      XA1_P => XA1_P,
      clk => clk,
      digit_select(7 downto 0) => digit_select(7 downto 0),
      dp => dp,
      reset => reset,
      seg(6 downto 0) => seg(6 downto 0)
    );
end STRUCTURE;
