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-- IP VLNV: xilinx.com:user:Seg_Display_16:1.0
-- IP Revision: 2

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY design_1_Seg_Display_16_0_0 IS
  PORT (
    seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    dp : OUT STD_LOGIC;
    an : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    digit_1 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_2 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_4 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_5 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_6 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_7 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    digit_8 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    clk : IN STD_LOGIC
  );
END design_1_Seg_Display_16_0_0;

ARCHITECTURE design_1_Seg_Display_16_0_0_arch OF design_1_Seg_Display_16_0_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_Seg_Display_16_0_0_arch: ARCHITECTURE IS "yes";

  COMPONENT Seg_Display_16 IS
    GENERIC (
      input_clk_freq : INTEGER;
      refresh_rate : INTEGER
    );
    PORT (
      seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
      dp : OUT STD_LOGIC;
      an : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      digit_1 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_2 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_4 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_5 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_6 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_7 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      digit_8 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
      clk : IN STD_LOGIC
    );
  END COMPONENT Seg_Display_16;
  ATTRIBUTE X_CORE_INFO : STRING;
  ATTRIBUTE X_CORE_INFO OF design_1_Seg_Display_16_0_0_arch: ARCHITECTURE IS "Seg_Display_16,Vivado 2015.4";
  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_Seg_Display_16_0_0_arch : ARCHITECTURE IS "design_1_Seg_Display_16_0_0,Seg_Display_16,{}";
  ATTRIBUTE CORE_GENERATION_INFO : STRING;
  ATTRIBUTE CORE_GENERATION_INFO OF design_1_Seg_Display_16_0_0_arch: ARCHITECTURE IS "design_1_Seg_Display_16_0_0,Seg_Display_16,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=Seg_Display_16,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,input_clk_freq=100000000,refresh_rate=50000}";
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
  U0 : Seg_Display_16
    GENERIC MAP (
      input_clk_freq => 100000000,
      refresh_rate => 50000
    )
    PORT MAP (
      seg => seg,
      dp => dp,
      an => an,
      digit_1 => digit_1,
      digit_2 => digit_2,
      digit_3 => digit_3,
      digit_4 => digit_4,
      digit_5 => digit_5,
      digit_6 => digit_6,
      digit_7 => digit_7,
      digit_8 => digit_8,
      clk => clk
    );
END design_1_Seg_Display_16_0_0_arch;
