2015.4:
 * Version 3.2
 * No changes

2015.3:
 * Version 3.2
 * Corrected the Alarm limits for VCCINT and VCCBRAM for -1L speedgrade devices.
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * IP delivers only Verilog example design files.

2015.2.1:
 * Version 3.1
 * No changes

2015.2:
 * Version 3.1
 * Corrected the Alarm limits for VCCINT and VCCBRAM for -2L speedgrade devices.

2015.1:
 * Version 3.0 (Rev. 7)
 * GUI Updates, no functional changes

2014.4.1:
 * Version 3.0 (Rev. 6)
 * No changes

2014.4:
 * Version 3.0 (Rev. 6)
 * Internal device family change, no functional changes

2014.3:
 * Version 3.0 (Rev. 5)
 * Added EXTERNAL_MUXADDR_ENABLE parameter to enable MUXADDR used for Dynamic Configuration for external mux mode
 * SIN, TRIANGLE and SQUARE stimulus generation in the range 0.1 KHz to 96 KHz. CSV file format to txt file conversion for simulation.

2014.2:
 * Version 3.0 (Rev. 4)
 * Fixed issue with VCCBRAM channel enablement in INIT_48 for sequencer mode

2014.1:
 * Version 3.0 (Rev. 3)
 * Internal device family name change, no functional changes
 * Corrected GUI enablement option in Default sequencer mode

2013.4:
 * Version 3.0 (Rev. 2)
 * No changes

2013.3:
 * Version 3.0 (Rev. 2)
 * Updated AXI4 Streaming FIFO depth from [1:1017] to [7:1020]
 * Added check to disable invalid Vauxp/Vauxn pairs for x*7z010clg225 Zynq device
 * Defined Vp/Vn and Vauxp/Vauxn as bus interfaces, no functional change
 * Added option in GUI to provide relative path for sim file, no functional change
 * Added a summary tab in the GUI, no functional change
 * Added support for Cadence IES and Synopsys VCS simulators
 * Reduced warnings in synthesis and simulation
 * Enhanced support for IP Integrator

2013.2:
 * Version 3.0 (Rev. 1)
 * Fixed CRITICAL WARNING for clock constraints on DCLK
 * Updated Life-Cycle status of devices

2013.1:
 * Version 3.0
 * Lower case ports for Verilog
 * Added AXI4STREAM interface support

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